Vlsi Technology, Inc.

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

David L Ganapol

Scott Wu

Gary L Small

Marc Jacobs

Tom Lim

Bruce Tirado

William Su

Arno G Marcuse

Michael Gonia

Robert P Zaldain

Reid T Hirata

A probe card for testing dies of a substrate during a wafer sort process includes a printed circuit board (PCB) and a test site arranged to connect respectively to one of the dies during a test cycle. The test site includes a first pin connecting band and a first pin set. The first pin connecting band is connected to the PCB. The first pin set is connected to the first pin connecting band and includes a pin configuration for a testing device to perform a first type of test on a first die. The test site includes only pins in the first pin set. A number of pins in the first pin set is less than a number of pins used to perform a second type of test on the first die. The second type of test is performed at a slower processing speed than the first type of test.

Multi-test type probe card and corresponding testing system for parallel testing of dies via multiple test sites

Embodiments of the present disclosure provide an apparatus configured to engage a device for testing the device via automatic test equipment. The apparatus includes a heat sink, wherein the heat sink comprises a plurality of fins extending from the heat sink, and wherein the heat sink is configured to engage the device. The apparatus further includes a heat conduction layer coupled to the heat sink, a first leg coupled to the heat conduction layer, and a second leg coupled to the heat conduction layer. The second leg is spaced apart from the first leg. A vacuum path is defined through (i) the heat conduction layer and (ii) the heat sink. The vacuum path permits the apparatus to engage the device to be tested by the automatic test equipment.

Heat sink blade pack for device under test testing

An improved method for transferring a semiconductor carrier tray is disclosed. The method herein provides for transferring a semiconductor carrier tray from a first location to a second location by first positioning a cap member to cover the mouth of at least one cup of a semiconductor carrier tray. The capping member contacts the uppermost surface of the cup wall. A partial vacuum is applied to the capped cup, and atmosphere is evacuated from the capped cup, adhering the semiconductor tray to the capping member. Movement of the capping member causes movement of the carrier tray from a first location to a second location. When the carrier tray has been positioned at its final destination, the vacuum is released causing separation of the carrier tray and the capping member. A vacuum cap apparatus is also disclosed.

Universal QFP tray transfer method

Test jig apparatus for testing an integrated circuit chip that suppresses build-up and subsequent discharge of electrical charge on the test jig apparatus or on the chip. The test jig apparatus includes a base of selected material having a top surface of the same general shape and dimensions as the chip to be tested. Preferably, the entire top surface of the base is electrically grounded. The base has two or more side surfaces with side surface planes that are approximately perpendicular to a plane defining the top surface of the base. Each side surface accepts a side plate, made of a selected material such as ULTIM, that can be attached to or removed from the base. The side plate material resists electrical charge buildup and subsequent discharge so that the chip being tested is not subjected to electrical discharge from this source. In another embodiment, the side plates are replaced by plates mounted on the top surface of the base.

Integrated circuit test jig

In a system for positioning a semiconductor chip package with respect to a testing surface, the distance between the package or the leads thereof and the testing surface is monitored while the package is pushed towards the testing surface. When the distance monitored falls below a certain value, the package is pushed further by a set distance. In this manner, good contact between the leads of the package and the contacts of the testing surface is achieved without destroying the coplanarity of the leads.

System for positioning a semiconductor chip package with respect to a

A method and apparatus for marking or erasing a marking on a semiconductor chip package having leads. The apparatus comprises a circular disk has many pockets on one surface near its circumference suitable for holding semiconductor chips. Each pocket has a pedestal rising from the bottom of the pocket and suitable for supporting the bottom portion of a semiconductor chip package. The edges of the pocket and the pedestal define between them space suitable for housing the leads of the package. The pedestal has a hole therein which can be evacuated so that the package is held to the pedestal by atmospheric pressure so that the top surface of the package may be marked or in marking thereon can be erased. Thus the package is held to the pedestal by sufficient force for the marking or erasing process. The leads of the package are therefore not bent or otherwise disturbed. Rotation of the disk allows the packages to be sequentially marked or erased.

Growing community of inventors

Scotts Valley, CA, United States of America

David L Ganapol