Micron Technology Incorporated

Varian Associates, Inc.

David L Chapek

Karl M Robinson

John T Moore

Fernando N Gonzalez

Randhir P Thakur

Randhir P S Thakur

Trung Tri Doan

Weimin Li

Kevin J Torek

Michael L Nuttall

Michael William Kissick

Susan Benjamin Felch

Ranshir P S Thakur

Tienyu Terry Sheng

Shamim Muhammad Malik

A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.

Semiconductor devices including a layer of polycrystalline silicon having a smooth morphology

The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure

The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross-section of which has a nail shape in cross-section.

Method for forming a self-aligned T-shaped isolation trench

In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made by depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing a sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.

Trench isolation for semiconductor devices

The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system. The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide. The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.

Integrated circuit formed by removing undesirable second oxide while minimally affecting a desirable first oxide

A thermal reflow processing system has a rotatable structure to which articles having a reflowable surface are attached. The structure is coupled to a drive motor which causes the structure to rotate at speeds which generate centripetal forces in excess of that of gravity. The system is equipped with at least one radiant heat source. As the articles are being subjected to a centripetal force, the surface is heated by the radiant heat source.

System for performing thermal reflow operations under high gravity conditions

Systems for performing thermal reflow operations under high gravity conditions

A thermal reflow processing system has a rotatable structure to which articles having a reflowable surface are attached. The structure is coupled to a drive motor which causes the structure to rotate at speeds which generate centripetal forces in excess of that of gravity. The system is equipped with at least one radiant heat source. As the articles are being subjected to a centripetal force, the surface is heated by the radiant heat source. In a preferred embodiment, the structure is a hermetically-sealable chamber which can be pressurized or evacuated. The articles, which may be semiconductor wafers, are positioned on the rotating structure such that the surface to be reflowed faces both the heat source and the structure's rotational axis. In the case of circular semiconductor wafers, the wafers are positioned such that the planar surface of each wafer is centered on and perpendicular to a radius of the cylindrical chamber. By performing the reflow operation while the chamber is spinning, high pseudo-gravitational forces can be generated which aid in planarization, void elimination, densification and in the filling of small aspect ratio contact via openings.

Method and apparatus for performing thermal reflow operations under high gravity conditions

In one aspect, the invention includes a semiconductor processing method of removing water from a material comprising silicon, oxygen and hydrogen, the method comprising maintaining the material at a temperature of at least about 100&deg; C., more preferably at least 300&deg; C., and at a pressure of greater than 1 atmosphere to drive water from the material. In another aspect, the invention includes a semiconductor processing method of forming SiO,having a wet etch removal rate of less than about 700 Angstroms/minute comprising: a) forming a layer comprising Si(OH),; b) maintaining the Si(OH),at a temperature of at least about 300&deg; C. and at a pressure of greater than 1 atmosphere to drive water from the Si(OH),; and c) converting the Si(OH),to SiO,, the SiO,having a wet etch removal rate of less than about 700 Angstroms/minute under the conditions of a buffered oxide etch utilizing 20:1 H,O:HF, at about atmospheric pressure and at a temperature of about 30&deg; C. In another aspect, the invention includes a method of forming a trench isolation region comprising: a) forming a trench within a substrate; b) forming a layer comprising Si(OH),within the trench and over the substrate; c) driving water from the layer comprising Si(OH),at a pressure of greater than 1 atmosphere; d) converting the Si(OH),to SiO,; and e) removing at least a portion of the SiO,.

Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers

Field oxide is formed using high pressure. Oxidation of field regions between active regions is accomplished in a two-step process. A first oxide layer is formed in the field region. Then, a second oxide layer is formed on the first oxide layer. The second oxide layer is formed at a pressure of at least approximately 5 atmospheres. In one embodiment, the first oxide layer is formed at atmospheric pressure using a conventional oxidation technique, such as rapid thermal oxidation (RTO), wet oxidation, or dry oxidation. In another embodiment, the first oxide layer is formed, at a pressure of approximately 1 to 5 atmospheres. Wet or dry oxidation is used for the oxidizing ambient. The first oxide layer is formed to a thickness of approximately 500 angstroms or less, and typically greater than 200 angstroms. Temperatures of approximately 600 to 1,100 degrees Celsius are used for the oxidation steps.

Method for forming oxide using high pressure

In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.

A method of forming trench isolated integrated circuitry on a substrate provides a substrate having a first insulating material within and projecting from an isolation trench and a second insulating material laterally proximate the first insulating material. The second insulating material is etched substantially selective relative to the first insulating material to expose substrate beneath the second insulating material. After the etching, a gate dielectric layer is formed over the exposed substrate. A transistor gate is formed over the gate dielectric layer. In but one other implementation, an oxide layer is thermally grown over a semiconductive substrate. An isolation trench is formed through the thermal oxide layer and the semiconductive substrate. Oxide is deposited within the trenches and formed to project outwardly relative to the thermal oxide. The thermally grown oxide is etched substantially selective relative to the deposited oxide to outwardly expose the semiconductive substrate and provide deposited oxide within the isolation trench which projects outwardly of the substrate. The semiconductive substrate and projecting deposited oxide have an interface therebetween which is substantially void of any recess of the deposited oxide below the semiconductive substrate. After the etching, gate oxide is grown over the substrate and the interface. A transistor gate is formed over the gate oxide over the semiconductive substrate.

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Nashua, NH, United States of America

David L Chapek