International Business Machines Corporation

David K Balkin

Sebastian Theodore Ventrone

John M Lauffer

Bernd Karl Appelt

Irving Memis

Robert Maurice Houle

Robin A Susko

Andrew Michael Seman

Ronald A Kaschak

Kenneth Torino

James Jens Hansen

Joseph Hromek

Magan S Patel

Lawrence C Alexander

A method of cache testing and fault correction is implemented subsequent to wafer dicing. Cache testing is moved from wafer level to the built-in self test (BIST) at machine level. The BIST is utilized along with cache redundancy for fault correction. The processor initiates a cache line test using BIST upon power-up. When the processor is powered up and the test mode pins are set for the array test, the array BIST test begins. The BIST traverses the array and tests each word line for hardware faults. Upon detection of a fault, the current address is stored in one of N fault address registers contained in the processor. These fault address registers are used to address redundant cache lines and therefore act as 'soft' fuses. The entire cache structure is traversed in this manner with the addresses of any line faults being stored. If the number of found faults, indicated by stored addresses, are less than the number of redundant fault lines, then the processor self test will proceed to the next test. However, if the number of faults exceed the maximum number N of redundant fault registers, then an error condition will be broadcast to either a set of pins or registers, and the cache will not be allowed to be enabled.

Soft fuses using bist for cache self test

Circuit boards or cards containing metallic layers on opposite major surfaces of a dielectric substrate whereby electrical and/or thermal interconnection between the metallic layers is provided in vias that extend through one of the metallic layers, and the dielectric substrate and into the other metallic layer.

Electrical and/or thermal interconnections and methods for obtaining such

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Mishawaka, IN, United States of America

David K Balkin