Lsi Corporation

Lsi Logic Corporation

David J Sturtevant

Bruce Joseph Whitefield

Duane B Barber

David A Abercrombie

Nima A Behkami

Ann I Kang

ChandraSekhar Desu

Jason W McNichols

A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.

Method for optimizing wafer edge patterning

A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

Yield profile manipulator

A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

Mask set for variable mask field exposure

A method of determining the distance from an edge feature to a wafer edge. The wafer is put onto an image acquisition tool, and images are captured and classified. Based on the coordinates of the images and their classifications, the distance between an edge feature and the wafer edge is determined. Reference marks can be etched into the wafer to facilitate the measurement. The measurement technique is objective, and can be used to minimize the edge exclusion ring as well as defects that originate from the edge of the wafer.

Wafer edge structure measurement method

A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.

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Gresham, OR, United States of America

David J Sturtevant