Integrated Device Technology, Inc.

David J Pilling

Raymond M Chu

Sik K Lui

Michael A Ang

Cesar A Talledo

Robert J Proebsting

Mario F Au

Larry D Johnson

Chuen-Der Lien

Anita M Hansen

Kar-chung Leo Lee

John R Mick

Jitesh Shah

Scott Revak

James Keener Fox

Ken Chan

Kevin W Glass

Diane Peng

Derek Huang

A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires.

Lead frame package

A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.

Behavioral modeling of high speed differential signals based on physical characteristics

In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

In-situ monitor of process and device parameters in integrated circuits

In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Output drive circuit that accommodates variable supply voltages

In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching.

High-speed, low-power level shifter for mixed signal-level environments

Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current surges, or power supply noise coupling through electro-static discharge (ESD) structures. In known systems, the ground supplies for the timing circuits are designed with power and ground supplies, separate from the core power and ground; although the ground supplies are connected via common Vsubstrate, they are separated from pad ring output driver power and ground supplies. In embodiments of the present invention, the PLL or DLL and core supplies are kept separate from the output driver power and ground supplies, providing for improved systems and methods that attenuate the effects of ground current surges from chip output drivers as they switch from logic highs to logic lows.

Circuits and methods that attenuate coupled noise

An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.

Integrated circuit systems and devices having high precision digital delay lines therein

Integrated circuit delay devices include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period. The ring oscillator signal may be generated by a ring oscillator having a relatively small number of stages and the time interval may be sufficiently long so that a large number of cycles of the ring oscillator signal may be counted over many periods of the clock signal.

Integrated circuit devices having high precision digital delay lines therein

Multi-phase clock generators include a master-slave flip flop that generates a second pair of clock signals having a second frequency in response to a first pair of clock signals having a first frequency greater than the second frequency. The master-slave flip-flop includes a master stage that is responsive to a first one of the first pair of clock signals and has a first pair of differential inputs and a first pair of differential outputs. A slave stage is also provided. The slave stage is responsive to a second one of the first pair of clock signals and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs that are cross-coupled and fed back to the first pair of differential inputs of the master stage.

Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times

Flip-flops include a master stage and a slave stage. The master stage is responsive to a first clock signal and has a first pair of differential inputs and a first pair of differential outputs. The slave stage is responsive to a second clock signal and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs from which true and complementary outputs (Q, QB) of the flip-flop are derived. If the flip-flop is a D-type flip-flop, the first pair of differential inputs receive true and complementary data signals (DATA, DATAB). If the flip-flop is a set-reset (S-R) flip-flop, the first pair of differential inputs receive set and reset signals (SET, RESET).

Integrated circuit flip-flops that utilize master and slave latched sense amplifiers

In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via, may be fabricated using processes generally used to fabricate normally sized vias and contact holes. The opening has a cross-sectional area A reduced by a factor of x relative to normally sized openings. Because the fusible interlevel interconnection has a reduced cross-sectional area, a programming current develops a destructive programming current density within fusible interlevel interconnection while current densities in coupled conductors, including normally sized vias and contacts, remain within long term reliability limits. Read/write circuitry connected to the fusible interlevel interconnection supports the programming current and supports a read current. The read current is regulated such that a responsive current density in a nonprogrammned fusible interlevel interconnection does not exceed long term reliability limits.

Electrically programmable interlevel fusible link for integrated circuits

An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup transistor and a pulldown transistor. The two pullup and pull down transistors are coupled in series between two drive transistor circuits. In one aspect of the invention, the pullup and pulldown drive transistor circuits provide momentary low impedance connection of the pullup and pulldown transistors to the respective pullup and pulldown voltage sources during the initial switching waveforms of the digital signal. After the initial switching of the digital signal, the pullup and pulldown drive transistor circuits provide precise V.sub.OH and V.sub.OL voltage output levels and provide high impedance filtering of voltage supply line and ground line noise. In another aspect of the invention, the high frequency response of the output is enhanced by auxiliary pullup and pulldown drivers in parallel with the pullup and pulldown output transistors. These auxiliary pullup and pulldown drivers reduce the switching time of the digital signal output to provide increased frequency response even in a high capacitance loaded environment.

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Los Altos Hills, CA, United States of America

David J Pilling