Synopsys, Inc.

David J Giramma

Thomas E Roth

Oliver W Kozber

David K Johnson

Michael G Robinson

Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent or processor, at the input pin to state elements such as D Flip-Flops. The interposition of the defer agent is handled by the simulator as follows. Defer agents schedule events related to input state changes on a special time or task queue which is not processed until after all other events have been executed for the current time, including any extra iterations caused by 0-delay scheduling activity. Defer agents or processors are placed in a simulation network just prior to one or more of the input pins of state elements, the effect of which is to delay events that normally would propagate to the input pin of a state element until all other normal simulation events are processed. Once the normal simulation events have been executed, the defer events are executed which permits the inputs of the state elements to change after other simulation events have been executed, thereby ensuring consistent evaluation of pin changes at state elements.

Digital simulator circuit modifier, network, and method

Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times. In accordance with a preferred embodiment of the invention, a set of rules is enforced by the logic processor during a digital logic simulation run to ensure that appropriate timing and constraint for the logic cell is maintained. Zero-delay timing is used across a collection of instances within a logic cell, thereby to ensure that all timing and constraint analysis is performed at cell boundaries. Timing is evaluated after all simulation activity for a given time frame has ceased, and such is done preferably by scheduling scrubber events that are executed as tasks on a defer queue that is processed at the end of the digital logic simulation activity.

Tool, system and method for dynamic timing analysis in a plural-instance

Method and apparatus for more efficiently using the undefined logic state and mixed multiple state abstractions is described. The method involves dividing gates into two groups: those that require an 8-state table (either because their inputs are sensitive to 8-state values or their output produces an 8-state value), and those that require only 4-state values (their inputs are insensitive to 8-state values and the output produces only 4-state values). The key to obtaining the advantages of the invention is the choice of the 4-state values. Previously, the 4-state values have been 0, 1, X, and Z. By the invented method and apparatus, the 4-state values are defined instead to be 0S, 1S, XS, and U. In the Multi-value Logic 9-state model (MVL-9), U is defined to be the uninitialized state, and thus it is a state that all instances need to process on their inputs and to produce as an output. The Z (or high-impedance) state, on the other hand, is used only for certain specialized gates--typically tri-state buffers--and so the Z state is used only rarely in digital logic simulation. By shifting the definition of the 4-state abstraction from (0, 1, X, Z) to (0S, 1S, XS, U), almost all gates may be included in the 4-state category, thus allowing higher pin counts for the average digital logic simulation. The invented method and apparatus nevertheless permits the interconnection of 4-state values and 8-state values, while placing the significant overhead of the latter on the rare use thereof. Preferably, both 4-state and 8-state directives--instructions to a downstream gate that tells the gate how to attain a new state--are provided by the invented method and apparatus, and the gate receiving such plural directives effectively decides whether to use the 4-state abstraction or the more expensive 8-state abstraction.

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Portland, OR, United States of America

David J Giramma