Si Bond L.l.c.

Memc Electronic Materials, Inc.

David I Golland

Robert A Craven

Ronald D Bartram

Ankur H Desai

Michael S Wisnieski

A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.

Edge stripped BESOI wafer

Process for stripping outer edge of BESOI wafers

A semiconductor wafer polisher of the present invention for polishing at least one semiconductor wafer to flatten a first face of the wafer and reduce the thickness of the wafer from an initial thickness t.sub.1 to a predetermined final thickness t.sub.2. The polisher comprises a first surface including a polishing surface portion, a second surface including a second surface portion, and a wafer carrier for holding the semiconductor wafer between the polishing surface portion and the second surface portion. At least one polishing limiter is between the first and second surfaces for limiting the reduction in thickness of the wafer. The wafer carrier and polishing limiter are integrally formed such that the polishing limiter and wafer carrier constitute a single unitary piece. The polishing limiter has at least one rubbing surface adapted for rubbing against one of the first and second surfaces and is sized and configured such that the rubbing surface is spaced axially from the one of the first and second surfaces when the semiconductor wafer has the thickness t.sub.1 and such that the rubbing surface rubs against the one of the first and second surfaces and the polishing limiter extends from the second surface to the first surface when the semiconductor wafer has the thickness t.sub.2. The polishing limiter has a greater resistance to polishing than that of the semiconductor wafer such that the polishing limiter prevents the polishing surface and the second surface portion from further moving axially toward each other when the polishing limiter extends from the second surface to the first surface to prevent the wafer from being reduced in thickness beyond the thickness t.sub.2.

Semiconductor wafer polisher and method

Growing community of inventors

Chesterfield, MO, United States of America

David I Golland