International Business Machines Corporation

Other

Advanced Technology Materials, Inc.

Varian, Inc.

Siemens Aktiengesellschaft

David Edward Kotecki

Katherine Lynn Saenger

William H Ma

Jeffrey P Gambino

Alfred Grill

Carl John Radens

Hua Shen

James H Comfort

Jenny Lian

Louis L Hsu

Gary Bela Bronner

Panayotis Constantinou Andricacos

Satish D Athavale

Richard Anthony Conti

Jack Allan Mandelman

Herbert Lei Ho

Laertis Economikos

Yun-Yu Wang

Wesley Charles Natzle

Peter C Van Buskirk

Klaus D Beyer

Robert B Laibowitz

Christopher Carr Parks

Jonathan Daniel Chapple-Sokol

Chienfan Yu

Mark A Jaso

Gerhard Kunkel

James A Fair

Raul E Acosta

Zu-Jean Tien

Son Van Nguyen

Jack Oon Chu

Alejandro Gabriel Schrott

Richard Stephan Wise

Andrew Herbert Simon

Thomas J Shaw

Stephen Mark Rossnagel

Rajarao Jammy

Paul Charles Jamison

Vishnubhai Vitthalbhai Patel

Steven G Barbee

Hiroyuki Akatsu

Scott David Halle

Martin Gutsche

Heon Lee

Seshadri Subbanna

Chang-Ming Hsieh

Robert Anthony Rita

Anwar Husain

John A Miller

Gregory Costrini

Jingyu Lian

Mukta S Farooq

Manu J Tejwani

Horatio Seymour Wildman

Peter Richard Duncombe

Justin W Wong

Fen Fen Jamin

Chenting Lin

Greg Costrini

Nirmal Chaudhary

Edward C Fredericks

Kurt A Olson

Brian Cunningham

Donald L Wilson

Youngjin Park

Jeffrey L Blouse

Steven P Zuhoski

Jerzy Kanicki

Shwu Jen Jeng

Nimal Chaudhary

Tsoring-Dih Yuan

Anthony J Ricci

Nicholas Nagel

Stephan E Lassig

Lee J Kimball

Joachim Nuetzel

Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

Contact plug formation for devices with stacked capacitors

The present invention discloses a multi-diameter electrical conductor for use as an embedded plug in a microelectronic device. The multi-diameter electrical conductor consists of a body portion which has a first diameter, and at least one neck portion in contact with the body portion that has at least a second diameter smaller than the first diameter. In a preferred embodiment, the multi-diameter conductor is a dual-diameter conductor providing electrical communication between an electrode and an active circuit element in a semiconductor structure and comprising a lower body portion and an upper neck portion. The conductive materials used in forming the body portion and the neck portion of the contact plug can be selected from doped polysilicon, refractory metals, metal silicides, low resistivity metals, noble metals and their alloys, adhesion layers, metallic diffusion barrier layers, and oxide and nitride diffusion barrier materials. In a preferred embodiment, the body portion is formed of a first conductive material while the neck portion is formed of a second conductive material. In an alternate embodiment, the body portion and the neck portion are formed of the same conductive material. In another alternate embodiment, the contact plug further includes an additional layer of a conductive material situated between the body portion and the neck portion formed of a material different than that used in forming the body portion and the neck portion. The additional layer of conductive material has a diameter not less than the diameter of the neck portion and not more than the diameter of the body portion.

Method for fabricating a dual-diameter electrical conductor

A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.

Method of fabricating a stack capacitor DRAM

A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.

Storage-capacitor electrode and interconnect

In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode. A method of removing the hard mask material without damaging the surrounding surface includes the steps of: depositing a soft mask photoresist material over the composite surface, including the hard masked covered noble metal electrode and the dielectric surface, in a manner such that the soft mask material is thinner over the region of the noble metal electrode; removing the portion of the soft mask material over the noble metal electrode leaving the soft mask material over the dielectric surface; etching the hard mask material with the soft mask material protecting the dielectric surface; and removing the remaining portion of the soft mask material.

Method for removal of hard mask used to define noble metal electrode

A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.

Method for simultaneously forming a storage-capacitor electrode and interconnect

A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO .

Hydrogen peroxide and acid etchant for a wet etch process

A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.

Semiconductor structure and manufacturing method

Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.

Retrograde openings in thin films

A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.

Capacitor stack structure and method of fabricating description

A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.

Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces

An overhanging separator structure with a post projecting from a surface which may be a substrate, an underlying layer on the surface, and a separator layer on the underlying layer, with the separator layer overhanging the underlying layer. A discontinuous film is then formed in a single process step having a first portion on the separator layer and a second portion on the post, the discontinuity caused by the overhanging separator layer. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Overhanging separator for self-defining stacked capacitor

DRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate

A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.

Easy to remove hard mask layer for semiconductor device fabrication

A structure and method for forming an integrated circuit structure including forming at least one transistor structure, forming at least one ferroelectric capacitor above the transistor structure, annealing the ferroelectric capacitor, and forming at least one conductive contact between the transistor structure and the ferroelectric capacitor.

Method for forming a ferroelectric capacitor under the bit line

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Hopewell Junction, NY, United States of America

David Edward Kotecki