Motorola Corporation

David E Lopez

Tomas Colunga

Jerry E Prioste

A logic circuit for testing the reliability of an ASIC includes an array circuit having a plurality of matrix arrays each having a plurality of inputs. The plurality of matrix arrays being positioned in a predetermined row and column of the array circuit and being responsive to a plurality of input signals applied thereto for providing a respective row and column output. A parity circuit responsive to the row and column outputs of the plurality of matrix arrays for causing an output signal at an output of the logic circuit to be in a first logic state whenever the row outputs of the plurality of matrix arrays are logically different, or whenever the column outputs of the plurality of matrix arrays are logically different. A stimulus circuit coupled to the plurality of inputs of the plurality of matrix arrays for supplying the plurality of input signals to exhaustively stimulate each one of the plurality of matrix arrays with all possible logic combinations. A verification circuit for verifying the operation of the parity circuit by stimulating the parity circuit with a predetermined logic sequence. The reliability and functionality of the ASIC can be determined by observing a frequency of the output signal supplied at the output of the logic circuit wherein the frequency of the output signal is a function of the number of defects occurring within the array circuit and the parity circuit.

Logic circuit for reliability and yield enhancement

A design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells for Application Specific Integrted Circuit gate array and standard cell libraries is provided. A single integrated circuit includes a plurality of cells or macros from the library. A Gray code generator provides a plurality of Gray code signals to the cells in response to a binary counter. The binary and Gray code signals stimulate each state of each cell. A multiplexed output indicates the functionality of each state.

Built-in self test method for application specific integrated circuit

A bidirectional switching circuit is provided for testing a large number of AC data paths of LSI macrocell arrays. The circuit includes a plurality of bidirectional pins, a first logic means, and a second logic means. The switching circuit may be used to deskew a general purpose LSI tester wherein any pin may be used for input or output and the pulse at any pin may be inverted. The second logic means, receiving signals on selected pins, initializes the first logic means thereby determining which pins may be used for testing the data path desired.

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Tempa, AZ, United States of America

David E Lopez