International Business Machines Corporation

David E Lackey

Steven Frederick Oakland

Paul Steven Zuchowski

Vikram Iyengar

Gary Douglas Grise

Donald Lawrence Wheater

Scott Whitney Gould

Douglas Willard Stout

Thomas R Bednar

Peter Anton Habitz

David James Hathaway

Michael Richard Ouellette

Chandramouli Visweswariah

Jinjun Xiong

Alvar Antonio Dean

Brion L Keller

Pamela Sue Gillis

Chandramouili Visweswariah

Sebastian Theodore Ventrone

Vladimir P Zolotov

Jeanne P Bickford

Kevin William Gorman

Steven Michael Eustis

Roger Paul Gregor

Mark R Taylor

Carl Frederick Barnhart

Peter Verwegen

William R Tonti

Sang Hoo Dhong

John Atkinson Fifield

John Edward Barth, Jr

Eric A Foreman

William Vincent Huott

Joseph Andrew Iadanza

John Maxwell Cohn

James Douglas Warnock

Darren Lane Anand

David W Milton

Susan K Lichtensteiger

Leon Jacob Sigal

Anthony D Polson

Douglas Wayne Kemerer

Larry Wissel

Leah M Pastel

Theodoros Anemikos

Louis Bernard Bushard

Jeffery Howard Oppold

Scott Alan Tetreault

Laura S Chadwick

Theodore M Levin

Robert W Bassett

Thomas M Lepsic

Paul H Bergeron

Peter O Jakobsen

Thomas A Stranko

Dennis F Ackerman

Keith M Carrig

Harold E Reindel

Henry R Farmer

Wendel Dieter

Bernd K F Koenemann

Bernd K F Koenermann

Gary G Hallock

George R Deibert

Salina S Chu

David R Bender

Robert G Sheldon

A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested 'at speed' during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

Method and device for selectively adding timing margin in an integrated circuit

A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

Test path selection and test program generation for performance testing integrated circuit chips

A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.

Disposition of integrated circuits using performance sort ring oscillator and performance path testing

A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Dense register array for enabling scan out observation of both L1 and L2 latches

Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Microcontroller for logic built-in self test (LBIST)

A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.

Method and apparatus for a robust embedded interface

A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

Hold transition fault model and test generation method

A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

LSSD compatibility for GSD unified global clock buffers

A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains.

Avoiding race conditions at clock domain crossings in an edge based scan design

Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.

Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method

A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.

Design structure and apparatus for a robust embedded interface

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Jericho, VT, United States of America

David E Lackey