Globalfoundries Inc.

David Doman

Mahbub Rashed

Suresh Venkatesan

Subramani Kengeri

Jongwook Kye

Scott D Luning

Marc Laurent Tarabbia

Navneet Jain

David C Pritchard

Tuhin Guha Neogi

Yunfei Deng

Chinh Nguyen

Scott C Johnson

Irene Y Lin

Jeff Kim

Qi Xiang

Dinesh Somasekhar

Guillaume Bouche

Yan E Wang

Ali Keshavarzi

Srikanth Balaji Samavedam

Jason Eugene Stephens

Juhan Kim

Yuansheng Ma

Ingolf Lorenz

Rod Augur

Seung-Hyun Rhee

James B Gullette

Xiang Qi

Marc Tarrabia

Steve Soss

Larry Ho

At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a standard cell

A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.

Pass-through contact using silicide

Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.

Methods of using a trench salicide routing layer

Disclosed herein are integrated circuit devices having stacked power supplies and methods of making such integrated circuit devices. In one example, the device includes a first power supply structure, a second power supply structure electrically isolated from the first power supply structure, wherein at least a portion of the second power supply structure is positioned vertically below at least a portion of the first power supply structure, wherein the first power supply structure is one of an interruptible or an uninterruptible power supply structure, while the second power supply structure is the other of the interruptible or the uninterruptible power supply structure, a plurality of constant-power circuits conductively coupled to whichever of the first or second power supply structure that is the uninterruptible power supply and a plurality of interruptible-power circuits conductively coupled to whichever of the first or second power supply structure that is the interruptible power supply.

Stacked power supplies for integrated circuit devices and methods of making the same

An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

Cross-coupling based design using diffusion contact structures

An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Integrating optimal planar and three-dimensional semiconductor design layouts

A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.

Software and method for via spacing in a semiconductor device

An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

Providing timing-closed FinFET designs from planar designs

One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same

A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Semiconductor device having contact layer providing electrical connections

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Austin, TX, United States of America

David Doman