International Business Machines Corporation

Globalfoundries Inc.

David C Thomas

Timothy Dooling Sullivan

Matthew D Moon

Jeffrey P Gambino

Max Gerald Levy

Gary L Milo

Daniel A Delibac

Zhong-Xiang He

Tom C Lee

William Joseph Murphy

Erick G Walton

Max L Lifson

Thomas J Hartswick

Ronald R Uttecht

Shawn A Adderly

Anthony C Speranza

Richard A Gilmour

Anthony K Stamper

James William Adkisson

Vincent James McGahay

Edward Crandal Cooney, Iii

William Thomas Motsiff

Eric Jeffrey White

Robert Michael Geffken

Christy Sensenich Tyberg

Jonathan Daniel Chapple-Sokol

Daniel Scott Vanslette

Charles F Musante

Yoba Amoah

Mark P Murray

Amanda L Piper

Steven S Williams

Christine A Leggett

Sruthi Samala

Elizabeth T Webster

John Edward Cronin

Timothy Charles Krywanczyk

Paul H Smith, Jr

Rock Nadeau

Joel M Sharrow

Brian M Czabaj

Mordehai Heiblum

Kenneth H Yao

Christina M Knoedler

Dean Allen Schaffer

Kevin G Petrunich

Edward Daniel Buker

Christine Ann Anderson

Gloria Jean Kerszykowski

Clark D Reynolds

Michael S Lube

Thomas F Curran, Jr

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Semiconductor device with metal extrusion formation

A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

Tsv wafer with improved fracture strength

Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

Controlled metal extrusion opening in semiconductor structure and method of forming

Methods of forming a TSV wafer with improved fracture strength

Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes patterning the material to expose portions of the backside of the wafer. The method further includes roughening the backside of the wafer through the patterned material to form a uniform roughness.

Uniform roughness on backside of a wafer

Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.

Semiconductor structures with metal lines

Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof

The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.

Fuse structure having crack stop void, method for forming and programming same, and design structure

A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAlliner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAlliner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAlliner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Electromigration resistant aluminum-based metal interconnect structure

A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

Single and multilevel rework

Growing community of inventors

Richmond, VT, United States of America

David C Thomas