International Business Machines Corporation

David C Ahlgren

Gregory Gower Freeman

Anna Wanda Topol

Francois Pagette

Basanth Jagannathan

Martin Revitz

Jack Oon Chu

Marwan H Khater

Richard Paul Volant

Wesley Charles Natzle

Seshadri Subbanna

Ryan Wayne Wuthrich

Christopher M Schnabel

Adam D Ticknor

Mary Joseph Saccamango

David A Sunderland

Kangguo Cheng

Guy M Cohen

Ramachandra Divakaruni

Christian Lavoie

Thomas N Adam

Tze-Chiang Chen

Gary Bela Bronner

Huajie Chen

Kathryn Turner Schonenberg

Steven G Barbee

William H Ma

Kenneth Jay Stein

Louis DeWolf Lanzerotti

Erick G Walton

Chienfan Yu

Paul Andrew Ronsheim

Fen Fen Jamin

Marc Waine Cantell

Shao-Fu S Chu

Russell C Lange

David Angell

Feng-Yi Huang

Robert E Bendernagel

Feng Yi Huang

A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved f, Fmax and drive current.

Bipolar transistor with isolation and direct contacts

A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.

Fully silicided extrinsic base transistor

The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border

A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the litho for the active area, in particular a DRAM cell with a vertical transistor.

Vertical device with optimal trench shape

Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films

An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling

A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

BiCMOS integration scheme with raised extrinsic base

A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit

A process for stripping thin layers of oxide such as sacrificial pad oxide employs etching chemistry that widens cracks to remove shallow cracks and limit the widening of deep cracks, thereby producing a final oxide surface on thick layers of oxide that is less rough than prior art methods and enabling the fabrication of oxide-filled trenches that have geometries and/or surface smoothness that were previously impossible.

Oxide strip that improves planarity

A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

Method for making heterojunction bipolar transistor with self-aligned

An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Image reversal process for self-aligned implants in planar

A method for fabricating a bipolar transistor having a base doping variation of less than 20% is disclosed. A polysilicon base contact bipolar transistor is formed up to the point just prior to the intrinsic base-emitter formation. The intrinsic base-emitter opening is then reactive ion etched through the polysilicon base contact layer down to and into a single crystal silicon body thereunder, whereby the surface of the single crystal silicon is damaged. A silicon dioxide layer is then grown on the exposed and damaged single crystal silicon to convert the damaged silicon surface into a silicon dioxide layer. The silicon dioxide layer is removed by chemical etching to expose undamaged single crystal silicon. A screen silicon dioxide layer 50 to 500 .ANG..+-.10%, e.g., 180 .ANG., is then formed on the thus exposed undamaged single crystal silicon. The intrinsic base region is then formed by ion implantation through the screen silicon dioxide layer, the emitter region is formed within the intrinsic base region and electrical contact is made to the various elements of the bipolar transistor.

Method for fabricating a bipolar transistor

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Wappingers Falls, NY, United States of America

David C Ahlgren