International Business Machines Corporation

David B Colavito

Nivo Rovedo

Phung T Nguyen

A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Method for low topography semiconductor device formation

A field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the FET includes an active semiconductor region defined upon a substrate, the active semiconductor region further having a mesa region formed therein. The FET also includes a gate formed within the active semiconductor region, the gate abutting the mesa region along one side thereof. The FET further includes a source region defined within a first area of the semiconductor region, the first region being located over an insulating layer, and a drain region defined within a second area of the semiconductor region, the second area also being located over the insulating layer. The first and second areas of the semiconductor region are located on opposite sides of the mesa region, and the insulating layer isolates the source region and the drain region from the substrate. In another exemplary embodiment, one of the source region or drain region is defined within a top surface of the mesa region.

Semiconductor device with junction isolation

In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the contacts, which are placed in an aperture cut into the shallow trench isolation.

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Rock Hill, NY, United States of America

David B Colavito