Micron Technology Incorporated

Intel Corporation

Lodestar Licensing Group LLC

David A Daycock

Justin B Dorhout

Kunal R Parekh

Martin Ceredig Roberts

John David Hopkins

Christopher J Larsen

Chet E Carter

Mohd Kamran Akhtar

Gordon A Haller

Matthew J King

Yushi Hu

Brett D Lowe

Richard J Hill

Qian Tao

Darwin A Clampitt

Indra V Chary

Anilkumar Chandolu

Prakash Rau Mokhna Rau

Barbara L Casey

Thomas George

Yoshiaki Fukuzumi

Jun Fujiki

Albert Fayrushin

Chandra S Tiwari

Matthew Park

Sri Sai Sivakumar Vegunta

Rithu K Bhonsle

John B Matovu

Jun Zhao

Woohee Kim

Jordan D Greenlee

Paul A Morgan

Kunal Shrotri

Minsoo Lee

Bharat Bhushan

Shawn D Lyonsmith

Dimitrios Pavlopoulos

Gowrisankar Damarla

Benben Li

Liu Liu

Narula Bilik

Leroy Ekarista Wibowo

Curtis R Olson

Giovanni Mazzone

Jonghun Kim

Purnima Narayanan

Raj K Bansal

Meng-Wei Kuo

Christian George Emor

Pratap Murali

Biow Hiem Ong

Srivardhan Gowda

Devesh Kumar Datta

Lingyu Kong

Chieh Hsien Quek

Subramanian Krishnan

Saniya Rathod

Venkata Satyanarayana Murthy Kurapati

Chii Wean Calvin Chen

Wing Yu Lo

Gowrisankar Damaria

Guoxing Duan

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.

Memory devices including strings of memory cells and related systems

Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

Microelectronic devices including pillars with partially-circular upper portions and circular lower portions, and related methods

A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.

Elevationally-extending string of memory cells and methods of forming an elevationally-extending string of memory cells

Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Integrated structures

Microelectronic devices including isolation structures protruding into upper pillar portions, and related methods and systems

A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

Forming terminations in stacked memory arrays

Methods of forming electronic devices, and related electronic devices

Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies

A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

Bond pad connection layout

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

Semiconductor device structures with liners

Growing community of inventors

Boise, ID, United States of America

David A Daycock