Micron Technology Incorporated

Daryl C New

Thomas M Graettinger

Brent A McClure

Trung Tri Doan

Eugene P Marsh

Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an embodiment, the DBCP film is deposited on the circuit layer to be etched. Then the DCBP film is confined to define an area of interest in the DCBP film in which hexagonal domains will eventually be formed. Such confinement can constitute masking and exposing the DCBP film using photolithographic techniques. Such masking preferably incorporates knowledge of the domain spacing and/or grain size of the to-be-formed domains in the area of interest to ensure that a predictable number and/or orientation of the domains will result in the area of interest, although this is not strictly necessary in all useful embodiments. Domains are then formed in the area of interest in the DBCP film which comprises a hexagonal array of cylindrical domains in a matrix. The film is then treated (e.g., with osmium or ozone) to render either the domains or the matrix susceptible to removal, while the other component is then used as a mask to etch either dots or holes in the underlying circuit layer.

Selective provision of a diblock copolymer material

In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.

Methods of etching insulative materials, of forming electrical devices, and of forming capacitors

Semiconductor structures formed using redeposition of an etchable layer. A starting material is etched and redeposited during the etch on a sidewall of a foundation. The foundation may be removed or may form an integral part of the structure. The starting material may contain one or more layers of material. The structures are adapted for a variety of capacitor structures.

Semiconductor structures formed using redeposition of an etchable layer

Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. A thick, planarized insulating layer is deposited over the bottom electrode and a contact via is opened in the insulating layer to exposed the bottom electrode. This via is filled with the dielectric material. A top conductive layer is deposited over the dielectric material, masked and etched to form the top conductive layer. This etch may simultaneously etch any portion of the dielectric layer overflowing the contact via.

Pre-patterned contact fill capacitor for dielectric etch protection

A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a first layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the first layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

Method of improving alignment signal strength by reducing refraction index at interface of materials in semiconductors

Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. An insulating diffusion barrier, such as LPCVD silicon nitride, is deposited over the bottom electrode and a via is opened in the silicon nitride to expose the bottom electrode. This via is filled with the dielectric material. In a disclosed embodiment, the dielectric material is deposited in solution form and crystallized in a high-temperature step. A top conductive layer is deposited over the dielectric material, masked and etched to form the top conductive layer. This etch may simultaneously etch any portion of the dielectric layer overflowing the contact via.

Dielectric etch protection using a pre-patterned via-fill capacitor

Method of improving alignment signal strength by reducing refraction

A method for forming a structure by redepositing a starting material on sidewalls of a foundation during an etch of the starting material.

Method for forming a structure using redeposition of etchable layer

Method of forming capacitor while protecting dielectric from etchants

A two-step method of low temperature oxidation of a ferroelectric layer followed by high temperature crystallization of the ferroelectric film to protect underlying semiconductor layers against high temperature oxidation which can cause the conductive layers thereof to become nonconductive. The thus provides a barrier layer on a semiconductor wafer, depositing a ferroelectric layer on the barrier layer, heating the semiconductor wafer at a temperature in a range of about 400.degree. C. to about 700.degree. C. in the presence of oxygen to oxidize the ferroelectric layer, and then heating the semiconductor wafer at a temperature in a range of about 700.degree. C. to about 900.degree. C. in a non-oxidizing ambient to crystallize the oxidized, ferroelectric layer.

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Meridian, ID, United States of America

Daryl C New