Micron Technology Incorporated

Intel Corporation

Darwin Franseda Fan

John David Hopkins

Manuj Nahar

Masihhur R Laskar

Fatma Arzum Simsek-Ege

Irina V Vasilyeva

Anish A Khandekar

Vassil N Antonov

Ashonita A Chavan

Sanjeev Sapra

Hung-Wei Liu

Srikant Jayanti

Jeffery B Hull

Albert Liao

Aurelio Giancarlo Mauri

James C Brighten

Xue-Feng Lin

Nicholas R Tapias

Kamal Kumar Muthukrishnan

Duane M Goodner

Zhuo Chen

Gordon A Haller

Shyam Surthi

Kunal Shrotri

Jerome A Imonigie

Changhan Kim

Michael Mutch

Devesh Dadhich Shreeram

Ali Moballegh

Junting Liu-Norrod

Sateesh Koka

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry

Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Single-crystal transistors for memory devices

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.

Transistor and methods of forming transistors

Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500&#xb0; C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.

Methods of forming crystalline semiconductor material, and methods of forming transistors

Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

Semiconductor structure formation

Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

Devices and methods including an etch stop protection material

Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

Flash memory cells, components, and methods

Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

3D memory

3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices

Growing community of inventors

Boise, ID, United States of America

Darwin Franseda Fan