Texas Instruments Corporation

Hitachi, Ltd.

Texas Instruments France

Darvin R Edwards

Siva Prakash Gurrum

Gregory Eric Howard

Donald Charles Abbott

Bernardo Gallegos

Rajiv Carl Dunne

Manu Joseph Prakuzhy

Luigi Colombo

Kunihiro Tsubosaki

Marie Denison

Ichiro Anjoh

Masahiro Ichitani

Archana Venugopal

Masood Murtuza

Matthew David Romig

Michael A Lamson

Masazumi Amagai

Katherine G Heinen

Junichi Arita

Gregory Barton Hotchkiss

Hiep Xuan Nguyen

Kazunori Hayata

Lim T Beng

Chai T Chong

Gerard Chauvel

Vikas I Gupta

Dominique D'Inverno

Ming J Hwang

Michael F Chisholm

Tz-Cheng Chiu

Reynaldo M Rincon

Kejun Zeng

Elizabeth G Jacobs

Cheryl Diane Hartfield

M'Hamed Ibnabdeljalil

Steve E Sparks

Gérard Chauvel

Viswanathan Sundararaman

Dominique D'inverno

Katherine E Heinen

Elizabeth E Jacobs

A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-&#xb0; K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Integration of backside heat spreader for thermal management

A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Semiconductor package having etched foil capacitor integrated into leadframe

A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.

In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads.

Method for contacting agglomerate terminals of semiconductor packages

A plastic package () in which a semiconductor chip () is adhesively () attached to a metal stripe () having an agglomerate structure, and electrically connected to bondable and solderable metal stripes () having particulate structures; metal stripes () are touching metal stripes () of agglomerate structure to form vertical stacks (); coats of solder () are welded to the agglomerate metal stripes (and).

Semiconductor device having agglomerate terminals

One embodiment of the invention is a semiconductor system () of arrays (, etc.) of packaged devices. Each array includes a sheet-like substrate (, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (, etc.), which adheres to the substrate, embeds the connected components. Metal posts (, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

Array-processed stacked semiconductor packages

In a method and system for evaluating sub-critical fatigue crack growth in a semiconductor device, a plurality of energy pulses generated by an energy source are repeatedly impinged onto the semiconductor device for a predefined time interval. The repeated impinging of the plurality of energy pulses induces a mechanical stress within the semiconductor device. The induced mechanical stress, maintained below a threshold and repeated for a predefined number of cycles, causes a formation of a sub-critical fatigue crack within the semiconductor device. A detector detects the presence of the sub-critical fatigue crack leading to a fatigue failure. A rapid determination of a pass or fail status for a fatigue test of the semiconductor device is made by comparing a total number of cycles to fatigue failure to a predefined benchmark.

Rapid method for sub-critical fatigue crack growth evaluation

A predictive power regulation apparatus and method that minimizes power and ground bounce in a logic device. The apparatus includes a predictor and a voltage or current smoothing device connected to the predictor. The voltage or current smoothing device outputs adjusted voltage or current to power and ground planes of the logic device. In one embodiment, the predictor includes an instruction scanner device and a look-up table connected to the instruction scanner device. The instruction scanner device determines the next instruction to be executed by the logic device. A voltage/current scheduling buffer connected to the look-up table contains voltage and current compensation and the time at which the voltage or current compensation should be requested from the voltage or current smoothing device. An alternative predictive power regulation apparatus is described that reduces power and ground bounce caused by the I/O buffer circuitry switching in the logic device.

Method and apparatus to minimize power and ground bounce in a logic device

A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die mounted on a substrate. A conductive layer is deposited in the at least one cavity that substantially fills the space between the at least one cavity and the at least one die when the lid is coupled to the substrate.

System and method for high performance heat sink for multiple chip devices

A metal interconnect structure () comprising a bond pad (), which has copper with at least 70 volume percent composed of crystal grains expanding more than 1 &#x3bc;m in their main direction, and 30 or less volume percent composed of crystal grains, which expand less than 1 &#x3bc;m in their main crystal direction. A body () of tin alloy is in contact with the bond pad.

Solder joints for copper metallization having reduced interfacial voids

A multiprocessor system () includes a plurality of processing modules, such as MPUs (), DSPs (), and coprocessors/DMA channels (). Power management software () in conjunction with profiles () for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation. Further, activity counters may be selectively enabled for specific tasks in order to obtain more accurate profile information.

Temperature field controlled scheduling for processing systems

A self-leveling heat sink includes a spring-arm device having at least one aperture and at least one spring-arm is coupled to a substrate. The substrate has at least one package mounted thereon, so that when the spring-arm device is mounted to the substrate the at least one package passes through the at least one aperture. A heat sink operable to remove heat from the at least one package has at least one heat sink post operable to receive a heat sink clip located at the distal end of each of the at least one spring-arms. Each of the at least one spring-arms extending from an inside edge of the at least one aperture and operable to couple the heat sink to the at least one package.

System and method for self-leveling heat sink for multiple height devices

Growing community of inventors

Garland, TX, United States of America

Darvin R Edwards