Taiwan Semiconductor Manufacturing Comp. Ltd.

Darryl Kuo

Chen-Hua Douglas Yu

Wen-Chih Chiou

Li-Hsien Huang

Tsang-Jiuh Wu

Cheng-Hung Chang

Chia-Lin Yu

Ebin Liao

Chun Hua Chang

Hsiang-Yi Wang

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto T, and Ris greater than R.

Semiconductor component having through-silicon vias

A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

Method of making a semiconductor component having through-silicon vias

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.

Semiconductor component having through-silicon vias and method of manufacture

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

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Hsinchu, Taiwan

Darryl Kuo