International Business Machines Corporation

Samsung Electronics Co., Ltd.

Sony Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Siemens Aktiengesellschaft

Other

Kabushiki Kaisha Toshiba

Infineon Technologies Ag

Applied Materials, Inc.

Sony Electronics Inc

Siemens Components, Inc.

Siemens Microelectronics Limited

Darryl D Restaino

John Anthony Fitzsimmons

Son Van Nguyen

Stephen McConnell Gates

Sarah L Lane

Chester T Dziobkowski

Alfred Grill

Timothy Joseph Dalton

Thomas M Shaw

Yun-Yu Wang

Michael Wayne Lane

Jia Lee

Kensaku Ida

Chih-Chao Yang

Lawrence Alfred Clevenger

Daniel C Edelstein

Griselda Bonilla

Shahab Siddiqui

James J Demarest

Johnny Widodo

Philip L Flaitz

Stefanie Ruth Chiras

James Edward Fluegel

Thomas H Ivers

James R Lloyd

Edward Paul Barth

Takeshi Nogami

Sampath Purushothaman

Andrew Herbert Simon

Christos Dimitrios Dimitrakopoulos

Stephen Mark Rossnagel

Vincent James McGahay

Donald Francis Canaperi

Jeffrey Curtis Hedrick

Vishnubhai Vitthalbhai Patel

Mahadevaiyer Krishnan

Christy Sensenich Tyberg

Stephan Alan Cohen

Eric Gerhard Liniger

Derren Neylon Dunn

Judith Marie Rubino

Horatio Seymour Wildman

Steven E Molis

Pavel Smetana

Richard O Henry

Sean P E Smith

Ann H McDonald

Pei-Ing Paul Lee

Bernd M Vollmer

Delores A Bennett

Bill Klaasen

Chih-Chien Liu

Soon-Cheon Seo

Hariklia Deligianni

Hsueh-Chung Chen

Jae Hun Kim

Hosadurga K Shobha

Terry Allen Spooner

Xiao Hu Liu

Satyanarayana Venkata Nitta

Erdem Kaltalioglu

Richard Anthony Conti

Emily R Kinser

Edward Crandal Cooney, Iii

Paul Charles Jamison

Alexandros T Demos

Panayotis Constantinou Andricacos

Kang Sub Yim

Kang-Wook Lee

Tong-Yu Chen

Ashima B Chakravarti

Nancy Anne Greco

Eric Peter Solecky

Lynne Marie Gignac

Tomio Katata

Mark Hoinkis

Erick G Walton

Gwo-Shii Yang

Jae-hak Kim

Peter Stevens Locke

Michael Beck

Ernest N Levine

Thomas F Houghton

Roger M Young

Karl Hornik

Keith Thomas Kwietniak

Eva Erika Simonyi

Chiung-Sheng Hsiung

Philippe Mark Vereecken

Vu Ngoc Tran Nguyen

Dean S Chung

Frank V Liucci

Chi-Hua Yang

Hideaki Aochi

Hans W Poetzlberger

Michael J Schade

Jonathan Levy

Timothy L Holmes

Steven Reiter

Christopher E Pepe

A method for managing a metrology system includes receiving a part, identifying, with a processing device, a part type associated with the part, retrieving, with the processing device, test rule logic associated with the part type from a database, retrieving, with the processing device, measurement data associated with the identified part type, processing, with the processing device, the measurement data, applying, with the processing device, the test rule logic to the processed measurement data to determine whether the part should be measured, outputting the part responsive to determining that the part should not be measured, and incrementing, with the processing device, a counter and saving a value of the counter in the database responsive to outputting the part responsive to determining that the part should not be measured.

Metrology management

A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.

Method for preventing backside defects in dielectric layers formed on semiconductor substrates

A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line ('BEOL') wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same

A chip is provided which includes a back-end-of-line ('BEOL') interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric ('ILD') layers which include a dielectric material curable by ultraviolet (&#x201c;UV&#x201d;) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

BEOL interconnect structures with improved resistance to stress

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO&#x2014; or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices

Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 &#x212b; to about 50 &#x212b; and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.

Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby

Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (&#x2266;2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

Minimizing low-k dielectric damage during plasma processing

An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

Void-free damascene copper deposition process and means of monitoring thereof

Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.

Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength

A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter 'SiCOH') in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, &#x2014;CH&#x2014; crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH+CHstretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCHbonding of greater than about 2.0, and a peak area for Si&#x2014;O&#x2014;Si bonding of greater than about 60%, and a porosity of greater than about 20%.

Advanced low dielectric constant organosilicon plasma chemical vapor deposition films

Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.

Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses

An aqueous seeding solution of palladium acetate, acetic acid and chloride.

Manufacturable CoWP metal cap process for copper interconnects

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

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Modena, NY, United States of America

Darryl D Restaino