Advanced Micro Devices Corporation

Globalfoundries Singapore Pte. Ltd.

Globalfoundries Inc.

Globalfoundaries Inc.

Globalfoudnries Singapore Pte. Ltd.

Darin A Chan

Minh Van Ngo

William George En

David Keating Foote

Pinghui Li

Ming Zhu

Fei Wang

Lu You

Danny Pak-Chum Shum

Douglas J Bonser

Mark W Michael

Scott Allan Bell

Wanbing Yi

Mark S Chang

Paul L King

Philip A Fisher

Mario M Pelella

Simon Siu-Sing Chan

Chih Yuh Yang

Marilyn I Wright

Paul Raymond Besser

Christopher F Lyons

Srikanteswara Dakshina-Murthy

Marina V Plat

Seshadri Ramaswami

Xinshu Cai

Jung-Suk Goo

Raymond T Lee

John G Pellerin

Qiang Chen

Jeffrey P Patton

Sriram Madhavan

Liying Zhang

Haiqing Zhou

Matthew S Buynoski

Steven C Avanzino

Sunil D Mehta

Thorsten E Kammler

Simon S Chan

Errol Todd Ryan

Fan Zhang

Yi Zou

Sey-Ping Sun

John Espinoza Sanchez, Jr

Susan H Chen

Handoko Linewih

Jacques J Bertrand

Diana M Schonauer

Pei-Yuan Gao

Yiang Aun Nga

Shunqiang Gong

Robert J Chiu

Ruchil Kumar Jain

Yuansheng Ma

Austin Frenkel

Wen-Jie Qi

Terri Jo Kitson

Subramanian N Venkatkrishnan

Donna Michael, Legal Representative

John Caffall

Kei-Leong Ho

Christy Mei-Chu Woo De La Girond'arc

The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

High-voltage devices integrated on semiconductor-on-insulator substrate

Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

Memory device with density-controllable dummy fill strategy for near-MRAM  periphery and far-outside-MRAM logic regions for embedded MRAM technology

Density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology and method for producing the same

Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.

Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures

Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a handle layer. A partial buried insulator overlies the handle layer and underlies the active layer, terminates at a buried insulator termination point, and includes an electrically insulating material. A substrate extension is adjacent to the partial buried insulator, where the substrate extension overlies the handle layer and underlies the active layer, and where the substrate extension directly contacts the partial buried insulator at the buried insulator termination point. The substrate extension includes a semiconductive material. A memory gate overlies the active layer.

Integrated circuits with flash memory and methods for producing the same

A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

Magnetism-controllable dummy structures in memory device

A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Body tie test structure for accurate body effect measurement

The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

Process for design of semiconductor circuits

According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.

Disposable spacer process for field effect transistor fabrication

Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

Methods for fabricating a semiconductor device on an SOI substrate

An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

Integrated circuit and method of manufacture

An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Selectable open circuit and anti-fuse element

A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

Semiconductor component and method of manufacture

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

Conversion of transition metal to silicide through back end processing in integrated circuit technology

Growing community of inventors

Campbell, CA, United States of America

Darin A Chan