Taiwan Semiconductor Manufacturing Comp. Ltd.

Luminescent Technologies, Inc.

Danping Peng

Daniel S Abrams

Junjiang Lei

Stanley Joel Osher

Chien-Jen Lai

Xin Zhou

Kenji Yamazoe

Kenneth Lik Kin Ho

Daniel Beylkin

Sagar Vinodbhai Trivedi

Fangbo Xu

Lin Ping Zhang

Zhiru Yu

Yuan Fang

Linyong Pang

Paul Rissman

Vikram Tolani

Yong Liu

Yan Feng

Kenneth L Ho

Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.

Sub-resolution assist features

A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

Machine learning based model builder and its applications for pattern transferring in semiconductor manufacturing

In a method of manufacturing a lithographic mask of an integrated circuit for semiconductor device manufacturing an optical proximity correction (OPC) process to a layout pattern of the integrated circuit is performed to produce a corrected layout pattern. An inverse lithographic technology (ILT) process to the corrected layout pattern is also performed to enhance the corrected layout pattern to produce an OPC-ILT-enhanced layout pattern of the lithographic mask. A first contour image associated with the OPC-ILT-enhanced layout pattern is generated when the OPC-ILT-enhanced layout pattern of the lithographic mask is projected on a wafer. The features of the generated first contour image are extracted. And a second contour image of a developed photo resist pattern on the wafer associated with the OPC-ILT-enhanced layout pattern as an output of a deep neural network is generated.

Methods of preparing photo mask data and manufacturing a photo mask

A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.

Multi-component kernels for vector optical image simulation

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Synchronized parallel tile computation for large area lithography simulation

A mask layout is received. An interaction-free mask model is applied to the mask layout. An edge interaction model is applied to the mask layout. The edge interaction model describes an influence due to a plurality of combinations of two or more edges interacting with one another. A thin mask model is applied to the mask layout. A near field is determined based on the applying of the interaction-free mask model, the applying of the edge interaction model, and the applying of the thin mask model.

Method of modeling a mask by taking into account of mask pattern edge interaction

A method of making a mask includes computing a mask volume correction matrix for a given mask layout to be used to perform a lithography process. The mask volume correction matrix represents a diffraction field for a predetermined thickness of a material of the mask. A simulated mask pattern is computed by applying the mask volume correction matrix to the given mask layout. The simulated mask pattern is provided to a mask making tool.

Lithographic mask correction using volume correction techniques

A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer.

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Fremont, CA, United States of America

Danping Peng