Texas Instruments Corporation

Danny R Cline

Theo J Powell

Kuong Hua Hii

Wah Kit Loh

Hugh Pryor McAdams

Francis Hii

Adin E Hyslop

Narasimhan Iyengar

Chok Y Hung

Siak Kian Lee

James M Garnett

Tek Yong Lim

Keat Peng Lee

Kuong H Hii

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A ROM logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST registerreceives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Built-in self-test arrangement for integrated circuit memory devices

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A Rom logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST registerreceives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

An integrated circuit has a built-in self-test (BIST) arrangement ( ). The built-in self-test arrangement includes a read only memory (ROM), ( ) that stores test algorithm instructions. A ROM logic circuit ( ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

An integrated circuit memory device includes a wordline stress mode arrangement and a storage cell initialization arrangement with the array of storage cells. In the wordline stress mode arrangement, a plurality of wordlines are run across the array. Each wordline is connected with the gates of transfer transistors of a different row of the storage cells. A decoder, responsive to a control signal, simultaneously applies a supply voltage to the wordlines. The supply voltage may be provided by a selectable magnitude external source. In the cell initialization arrangement, a plurality of complementary pairs of bitlines are run across the array. Each complementary pair of the bitlines interconnects with the storage cells in a separate column of the array. A precharge circuit is arranged for precharging the bitlines to a precharge voltage. a precharge disabling circuit, responsive to the control signal, disables the precharge circuit from applying the precharge voltage and supplies an alterntive voltage to the pairs of bitlines. A separate amplifier is connected with each separate pair of complementary bitlines. A control circuit, responsive to the control signal, disables operation of the amplifiers when the alternative voltage is supplied to the pairs of bitlines. Considerable testing time can be saved. Burn in stress testing can be eliminated.

Wordline stress mode arrangement a storage cell initialization scheme test time reduction burn-in elimination

A test enable control for a built-in self-test of a memory device is provided. In one embodiment of the present invention, a test enabling system is provided. The test enabling system comprises an enable test circuit (62), a plurality of test algorithms stored in a read only memory (72) and a program counter (66) operable to control the execution of the test algorithm. The first instruction of each test is a jump test enable instruction (130) comprising a jump test instruction and an address in the read only memory (72) corresponding to the next test algorithm. The enable test circuit (62) is operable to signal to the program counter (66) if a particular test algorithm is enabled.

Test enable control for built-in self-test

Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n, 32.sub.0 -32.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (FIG. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay.

Apparatus and method for a programmable interval timing generator in a

A short disturb test algorithm for built-in self-test is provided. The short disturb test (108) initially writes a background pattern to all cells in a memory array (24). After verifying the background pattern was written, the opposite of the background pattern is written to a single row of the memory array for a fixed time. After that fixed time has elapsed, the original background pattern is written to the row. The memory array is then refreshed and the next row is written to. After all rows have been written to, the memory array (24) is checked for failures.

Short disturb test algorithm for built-in self-test

A read-only memory (ROM) embedded mask release number for a built-in self-test of a memory device is provided. A synchronous dynamic random access memory (10) comprises a conventional memory (12) and a built-in self-test arrangement (14). The built-in self-test arrangement (14) includes a read only memory (ROM) (72) which stores a plurality of algorithms. Each algorithm is comprised of a series of array access instructions (140) and program access instructions (142). The last instruction in ROM (72) is an idle instruction (120). Associated with idle instruction (120) is an identification number (132). Once stored in ROM (72), the identification number (132) can be read without the use of additional equipment.

ROM embedded mask release number for built-in self-test

A data invert jump instruction test for a built-in self-test of a memory device is provided. The data invert system comprises a read only memory (72) operable to store a plurality of test algorithms wherein at least one of the test algorithms includes a data invert jump instruction (160). Also included is a data invert circuit (178) coupled to the read only memory (72) and a toggle register (188) within the data invert circuit (178). The toggle register (188) is set to one when the data invert jump instruction (160) occurs for the first time in the test algorithm. This causes the data invert circuit (178) to output the inverse of the data inputted through the data invert circuit (178).

Data invert jump instruction test for built-in self-test

In a built-in-self-test (BIST) unit or a memory unit, an address limits unit is provided which, prior to initiation of the test procedures, has start and stop addresses stored therein. Upon the initiation of the test procedures by the BIST unit, the start address of the address limits unit is transferred to the address counters units wherein the start address serves as the initial test address. The stop address is transferred to the address counters unit wherein the stop address will be compared with the current address. When the stop address and the current address match, the test procedure being executed by the BIST unit will be terminated. In this manner, any subarray in the memory unit can be selected for test.

Apparatus and method for subarray testing in dynamic random access

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150) comprises an external clock source (152) and an internal clock source (177). A first multiplexer (164) is provided and has the external clock source (152) and the internal clock source (177) as data inputs and an internal clock selection bit value (B.sub.-- CLKMUXB 176) as a data select input. A second multiplexer (156) having the external clock (152) and the output of the first multiplexer as data inputs and a data select input (BCLK.sub.-- EN) based on whether a self-test mode is activated (BIST.sub.-- EN) and the internal clock selection bit value (B.sub.-- CLKMUXB) is also provided. The external clock source (152) or internal clock source (177) is selected based on the value of the internal clock selection bit value (B.sub.-- CLKMUXB 176) and whether the self test mode is activated (BIST.sub.-- EN).

Internal/external clock option for built-in self test

Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n,32.sub.0 -=.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a fist embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (FIG. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay.

A semiconductor random access memory having a complex topology is provided with ROM unit storing every potential row data pattern to be entered in the storage cell array during a test procedure, a variable step address generator, a comparator mechanism, and a control unit. In response to signals from the control unit, the variable step address generator enters each row data pattern at appropriate addresses determined by the periodicity of the complex topography. The variable step address generator is then used to retrieve stored data groups from addresses used to store each ROM data pattern. The retrieved data groups are compared with the ROM data pattern used as a template for the stored data group. A record of the comparison errors can be stored in an erasable memory unit.

Growing community of inventors

Plano, TX, United States of America

Danny R Cline