Freescale Semiconductor,inc.

Motorola Corporation

Daniel T Pham

Bich-Yen Nguyen

Ramachandran Muralidhar

Sufi Zafar

Chitra K Subramanian

Leo Mathew

Michael Alan Sadd

Alexander Barr

Ted R White

Sucharita Madhukar

Veeraraghavan Dhandapani

Xiaoqiu Huang

Amanda M Kroll

Anne M Vandooren

A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Power MOSFET with a gate structure of different material

A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.

LDMOS with channel stress

A method for forming a polysilicon FinFET () or other thin film transistor structure includes forming an insulative layer () over a semiconductor substrate (). An amorphous silicon layer () forms over the insulative layer (). A silicon germanium seed layer () forms in association with the amorphous silicon layer () for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (). During the annealing step, silicon germanium seed layer (), together with silicon germanium layer (), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (), drain (), and channel () regions are formed within the polysilicon layer. A double-gated region () forms in association with source (), drain (), and channel () to produce polysilicon FinFET ().

Method for forming a double-gated semiconductor device

A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements ( ) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer ( ) upon which a first gate insulator ( ) is formed. A plurality of pre-fabricated isolated storage elements ( ) is then deposited on the first gate insulator ( ). This deposition step may be accomplished by immersion in a colloidal solution ( ) that includes a solvent and pre-fabricated isolated storage elements ( ). Once deposited, the solvent of the solution ( ) can be removed, leaving the pre-fabricated isolated storage elements ( ) deposited on the first gate insulator ( ). After depositing the pre-fabricated isolated storage elements ( ), a second gate insulator ( ) is formed over the pre-fabricated isolated storage elements ( ). A gate electrode ( ) is then formed over the second gate insulator ( ), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region ( ) and a drain region ( ) are then formed in the semiconductor layer ( ) such that a channel region is formed between underlying the gate electrode ( ).

Memory device and method for using prefabricated isolated storage elements

Growing community of inventors

Austin, TX, United States of America

Daniel T Pham