Micron Technology Incorporated

Micron Semiconductor, Inc.

Daniel R Loughmiller

Kevin G Duesman

Joseph C Sher

Wen Qian Li

Mark R Thomann

Scott E Schaefer

Stephen L Casper

Stephen R Porter

Timothy B Cowles

Tyler J Gomm

Scott Eugene Smith

William F Jones

Roland Ochoa

Ross E Dermott

Travis E Dirkes

Greg A Blodgett

Reshmi Basu

Ryan G Fisher

Arvin Daniel A Daguro

Noel Marquez

Kenneth Koenig

A method includes performing a first operation to program data to a group of memory cells of a memory device, wherein the data comprises host data and a bit pattern indicative of a first temperature of the group of memory cells and receiving a signal to perform a second operation to read the host data from the group of memory cells. The method further includes determining, responsive to receipt of the signal, whether a second temperature of the group of memory cells is outside a threshold temperature differential that is based on the bit pattern indicative of the first temperature of the group of memory cells, applying a voltage offset signal to the group of memory cells responsive to a determination that the second temperature of the group of memory cells is outside the threshold temperature differential, and performing the second operation to read the host data from the group of memory cells subsequent to application of the voltage offset signal to the group of memory cells.

Temperature differential-based voltage offset control

A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The voltage control circuit includes a clamp circuit having a plurality of voltage regulation devices, typically diodes. The voltage regulation devices control an output of the clamp circuit. A voltage regulator is electrically coupled to the clamp circuit and generates a first control signal based upon the output of the clamp circuit. A charge pump then receives the control signal from the voltage regulator, and, based on the value of the control signal, the charge pump generates the test supply voltage. At least one bypass device is connected to at least one of the plurality of voltage regulation devices. The bypass device is activated following the certification of the semiconductor device. Once activated, the bypass device bypasses the respective voltage regulation device from the clamp circuit, which limits the output of the clamp circuit. The voltage regulator then generates a second control signal based upon the limited output of the clamp circuit. The second control signal is provided to the charge pump to generate the operational supply voltage.

Clamp circuit with fuse options

A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or the discharge line, the match detection circuit demonstrates whether it can overcome the applied loads.

Circuit and method for configuring CAM array margin test and operation

A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

Communication device for a logic circuit

A method for passing a voltage between an internal node inside a memory device and an external pin outside the memory device. The method includes passing an internal voltage from the internal node to the external pin during a read mode. The method also includes passing an external voltage from the external pin to the internal node during a force mode.

Circuit and method for measuring and forcing an internal voltage of an integrated circuit

A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.

Controller for delay locked loop circuits

A ternary CAM memory device is disclosed which comprises a pair of complementary compare lines, a pair of complementary bit lines, and a unique four transistor two capacitor circuit.

High density dynamic ternary-CAM memory architecture

An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

Method of reducing standby current during power down mode

A content addressable memory (CAM) cell which has a split word line scheme and having binary and ternary storage capability. The cell has a pair of storage devices, a comparing circuit, a pair of memory access devices having gates controlled by respective word lines, a pair of bit lines for writing to and reading from the storage devices, or pair of search lines. Furthermore, the dynamic CAM cell utilizes a folded bit line architecture with a single sense amplifier sensing inputs from the pair of bit lines.

Split word line ternary CAM architecture

Method for contact pad isolation

A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

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Boise, ID, United States of America

Daniel R Loughmiller