International Business Machines Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Daniel Mark Nelson

Derick Gardner Behrends

Travis Reynold Hebig

Todd Alan Christensen

Michael Launsbach

Chad Allen Adams

Jesse Daniel Smith

Peter Thomas Freiburger

Harold Pilo

George Maria Braceras

Vinod Ramadurai

Jeffrey Milton Scherer

Richard John Stephani

Ryan Charles Kivimagi

Write assist circuitry is disclosed to assist a memory device in changing logical states during a write operation. The write assist circuit includes write assist circuits which can be coupled to a shared boost capacitor to provide write assistance to the memory device. The write assist circuit includes boost switch circuit to selectively couple one or more of the write assist circuits and the shared boost capacitor. The one or more write assist circuits, when coupled to the shared capacitor, provide negative bitline assistance by selectively driving one of its corresponding bitlines pairs to be negative during a write operation.

Method and apparatus for selective write assist using shared boost capacitor

A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

Layout to minimize FET variation in small dimension photolithography

A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.

Single cycle data copy for two-port SRAM

A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Data security for dynamic random access memory using body bias to clear data at power-up

A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.

Implementing RC and coupling delay correction for SRAM

A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled inverters.

Data dependent SRAM write assist

A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines.

Data security for dynamic random access memory at power-up

A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.

Method and apparatus to limit circuit delay dependence on voltage for single phase transition

A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.

Single supply sub VDD bit-line precharge SRAM and method for level shifting

A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.

Delay chain burn-in for increased repeatability of physically unclonable functions

A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report.

Assessing resources required to complete a VLSI design

A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.

Implementing boosted wordline voltage in memories

An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.

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Rochester, MN, United States of America

Daniel Mark Nelson