Texas Instruments Corporation

Daniel Joseph Stillman

Margaret Simmons-Matthews

James L Oborny

Norman Armendariz

William John Antheunisse

Ramyanshu Datta

Kenneth Michael Butler

Jeff A West

Cheryl Diane Hartfield

Nancy R Ota

A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate

A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Through carrier dual side loop-back testing of TSV die after die attach to substrate

One embodiment of the invention is a method for evaluating a material such as low-k dielectric, by a stress-generating test tool such as a needle. The evaluation object is shaped as a stack of adhering layers: low-k dielectric, first metal (preferably copper), barrier metal (preferably tantalum nitride), and second metal (preferably aluminum). A numerical correlation is established between a cracking in the barrier metal layer caused by probing and a damage in the layer of insulating material-to-be-tested. A predetermined number of locations of the top metal layer is selected for the probing step comprising touch-down, applying force, and lifting is repeated so that the number of repeats provide a pre-determined statistical confidence level. The top metal layer is then removed by a chemical etch solution so that the etch solution also penetrates into any stress-created cracks of the barrier metal layer underneath the imprints, and further dissolves a portion of the first metal layer, generating cavities in the first metal layer. The occurrence of all first metal cavities is recorded and correlated with the probing.

Statistical method for identifying microcracks in insulators

An apparatus for electrical testing having probes () constructed of metal elements () of about equal size bonded together in substantially linear sequence. Further an insulating holder () having first and second surfaces and a plurality of metal-filled vias () traversing the holder from the first to the second surface; the vias form contact pads on the first and second surfaces. The contact pads () of the first holder surface have a probe attached so that the probe is positioned about normal to the surface. A sheet () of resilient insulating material, which has first and second surfaces and a thickness traversed by a plurality of conducting traces (), has its first sheet surface attached to the second holder surface so that at least one of the traces contacts one of the contact pads, respectively, to provide an electrical path to the second sheet surface. A printed circuit board, suitable for insertion into an electrical test apparatus, is attached to the second sheet surface so that a continuous electrical path is established from the apparatus to each of the probes.

Growing community of inventors

Garland, TX, United States of America

Daniel Joseph Stillman