At&t Bell Laboratories

Research Triangle Institute

Daniel J Vitkavage

David P Favreau

Kurt George Steiner

Robert J Markunas

Ronald A Rudder

Min-Liang Chen

Cheryl Anne Bollinger

Gaius G Fountain

Sunil Hattangady

Jane A Swiderski

Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

Integrated circuit with planar dielectric layer

A semiconductor device including a single crystal semiconductor host material having a surface; an ultrathin pseudomorphic single crystal epitaxial interlayer formed on the surface of the host material, wherein the interlayer is formed of a material and has a thickness selected so that the material of the interlayer is elastically deformed on the surface of the host material to match the lattice constant of the interlayer material with the lattice constant of the host material; and a further material incompatible with the host material when interfaced directly with the host material, but compatible with the interlayer, provided on the interlayer and thereby interfaced with the host material to perform a predetermined function with respect to the interlayer and the host material. In a preferred embodiment, the host material is a material selected from the group consisting of Ge, GaAs, InSb, InP, group II-V compounds and alloys thereof; the interlayer material is formed of pseudomorphic silicon, having a thickness of approximately 10 .ANG. and the further material is formed of SiO.sub.2 or a conductive material.

Semiconductor device having a semiconductor substrate interfaced to a

An integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric is formed to cover the active regions of a transistor and raised topographic features such as a gate runner. The upper level of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows are opened in the bilayer dielectric by etching through the upper level of the dielectric, stopping on the lower level of the dielectric. Then the etch procedure is continued to etch through the lower level of the dielectric.

Method of etching for integrated circuits with planarized dielectric

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Zionsville, PA, United States of America

Daniel J Vitkavage