Acorn Technologies, Inc.

Atomera Incorporated

Acorn Semi, LLC

Synopsys, Inc.

Daniel J Connelly

Daniel E Grupp

Robert J Mears

Richard Burton

Paul A Clifton

Marek Hytha

Hideki Takeuchi

Carl M Faulkner

Nyles Wynn Cody

Robert John Stephenson

R Stockton Gaines

Dmitri Choutov

Erwin Trautmann

Andreas Goebel

Vaishali Ukirde

Carl A Faulkner

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

Vertical semiconductor device with enhanced contact structure and associated methods

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Insulated gate field effect transistor having passivated schottky barriers to the channel

A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.

Method for making a semiconductor device including enhanced contact structures having a superlattice

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

Method for making a FINFET having reduced contact resistance

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance

A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1&#xd7;10atoms/cmor greater.

Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

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Redwood City, CA, United States of America

Daniel J Connelly