Vlsi Technology, Inc.

Daniel D Siems

Judy U Galloway

Pierre Leroux

Anthony Sayka

Stacy W Hall

Edward R Vokoun, Iii

Bryan D Schmidt

Clayton Lantz

Henry B Taylor, Iii

A method and process for reducing edge-related defects. The present invention comprises the steps of calibrating multiple process units such that the multiple process units are equally referenced with respect to an edge of a semiconductor wafer. The calibrated multiple process units are then utilized to precisely control respective termination distances of deposited substrate layers with respect to the edge of the semiconductor wafer. Furthermore, the deposited substrate layers are selectively stacked in manner which prevents semiconductor wafer edge-related defects. In so doing, the present claimed invention increases semiconductor device yields.

Wafer edge sealing

Method and apparatus for detecting the presence of selected types of defects, such as chemical stains from a liquid photoresist material or a liquid dielectric material, on a non-visible chosen surface of a semiconductor water that has undergone at least one processing step. In one embodiment, a support substrate for, the wafer is provided that has a highly reflecting surface adjacent to the chosen surface. The reflecting surface and the chosen surface are moved apart, and the chosen surface is illuminated with light to form an optical image of the chosen surface. The optical image of the chosen surface is reflected in the reflecting surface, and the reflected optical image is examined for the presence of selected types of defects. In another embodiment, a portion of this reflecting surface is initially contiguous to the chosen surface. A selected defect, if any, on the chosen surface changes a surface characteristic of the reflecting surface so that the presence of this defect on the chosen surface is visually perceptible on the reflecting surface.

Semiconductor wafer defect monitoring

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Boerne, TX, United States of America

Daniel D Siems