Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

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S.o.i.tec Silicon on Insulator Technologies

Commissariat a L'energie Atomique

France Telecom

France T&eacute;l&eacute;com

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Etablissement Autonome De Droit Public: France Telecom

Etat Francais Represente Par Le Minitre Des Ptt, Centre National

Daniel Bensahel

Yves Campidelli

Caroline Hernandez

Thomas Skotnicki

Bruno Ghyselen

Aomar Halimaoui

Didier Dutartre

Maurice Rivoire

Fran&ccedil;ois Martin

Olivier Kermarrec

Oliver Kermarrec

Yves Morand

Michel Haond

Vincent Cosnier

Laurent J Vallier

Jorge Regolini

Bernard Schaub

Jean Marine

Jean-Claude Pfister

Jorge L Regolini

Louis Revoil

Jean-Pierre Colinge

Bénédicte Osternaud

A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.

Method for making a semi-conducting substrate located on an insulation layer

A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

Method for forming integrated circuits on a strained semiconductor substrate

A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Single-crystal semiconductor layer with heteroatomic macro-network

Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.

Process for transferring a layer of strained semiconductor material

The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Single-crystal semiconductor layer with heteroatomic macronetwork

A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.

Electronic component manufacturing method

A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness. A first wafer having a strained layer of a semiconductor material on a matching layer is provided, with the semiconductor material having a first lattice parameter corresponding to a relaxed state and a first critical thickness corresponding to the first strained state, and the first thickness is less than the first critical thickness, The matching layer has a matching lattice parameter that is sufficiently different than the first lattice parameter to retain the strained layer in the strained state, The strained layer is transferred to a receiving substrate selected to provide the transferred strained layer with a second critical thickness that is greater than the first critical thickness, and additional semiconductor material is grown on the transferred strained layer to provide a second thickness that is greater than the first critical thickness and less than the second critical thickness, The invention also relates to the semiconductor structures that can be produced by the process.

A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.

Heteroatomic single-crystal layers

The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.

A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer () of silicon or of a silicon/germanium alloy on a layer () of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.

Process for fabricating strained layers of silicon or of a silicon/germanium alloy

A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of SiGe, where 0.5&#x3c;x&#x2266;1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).

Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material

A method for growing a single-crystal region of a III-V compound on a surface corresponding to a crystallographic plane of a single-crystal silicon substrate, including the steps of growing by epitaxy on the substrate a single-crystal germanium layer; etching in a portion of the thickness of the germanium layer an opening, the bottom of which corresponds to a single surface inclined with respect to the cristallographic plane or to several surfaces inclined with respect to the cristallographic plane; and growing the single-crystal III-V compound on the bottom of the opening.

Growth of a single-crystal region of a III-V compound on a single-crystal silicon substrate

A transistor is located on a base layerresting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate, a first strained silicon layerresting on the base layer, surmounted by a buried insulating layer, surmounted by a second strained silicon layerextending between the source S and drain D regions.

Growing community of inventors

Grenoble, France

Daniel Bensahel