International Business Machines Corporation

Globalfoundries Inc.

Dan Mihai Mocuta

Brian Joseph Greene

Huajie Chen

Anda C Mocuta

Huilong Zhu

Arvind Kumar

Byeong Yeol Kim

Devendra K Sadana

Bruce Bennett Doris

Effendi Leobandung

Carl John Radens

Dureseti Chidambarrao

Meikei Ieong

Diane Catherine Boyd

Paul Andrew Ronsheim

Ricky S Amos

Richard J Murphy

Stephen W Bedell

Kevin K Chan

Judson Robert Holt

Herbert Lei Ho

Ravikumar Ramachandran

Renee Tong Mo

Henry K Utomo

Werner A Rausch

Augustin J Hong

Colin J Brodsky

Chienfan Yu

Mahender Kumar

Wenjuan Zhu

Michael Abramovich Gribelyuk

Woo-Hyeong Lee

David M Rockwell

Ryan Matthew Mitchell

Anne C Friedman

Garrett W Oakley

Stephan W Bedell

Huajie c/o Ibm United Kingdom Ltd Chen

A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.

FinFET with constrained source-drain epitaxial region

A self-aligned strap structure can be formed by forming trench capacitors and overlying trench top conductive material portions. End portions of fin mask structures overlie portions of the trench top conductive material portions. A dielectric spacer is formed around each end portions of the fin mask structure to cover additional areas of the trench top conductive material portions. An anisotropic etch is performed to recess portions of the trench top conductive material portions that are not covered by the fin mask structures or dielectric spacers. Conductive strap structures that are self-aligned to end portions of semiconductor fins are formed simultaneously with formation of the semiconductor fins. Access fin field effect transistors can be subsequently formed.

Self-aligned laterally extended strap for a dynamic random access memory cell

A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.

A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack.

Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device

A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.

Multi-height multi-composition semiconductor fins

Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. Control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.

High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be SiGeZ, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

MOSFET with super-steep retrograded island

A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550&#xb0; C.-700&#xb0; C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH.

Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density

An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.

Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel

Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets

Structure and method for manufacturing MOSFET with super-steep retrograded island

Growing community of inventors

Lagrangeville, NY, United States of America

Dan Mihai Mocuta