Texas Instruments Corporation

Dan M Mosher

Taylor R Efland

Joe R Trogolo

David R Cotton

Cornelia H Blanton

Larry Latham

Keith Edmund Kunz

Sameer P Pendharkar

Charvaka Duvvury

Bob Todd

Seetharaman Sridhar

David Barry Scott

Jozef C Mitros

Chin-Yu Tsai

Alec James Morton

Peter Chia-cu Mei

Sam Shichijo

A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness&#x3c;the second thickness. A substrate having a semiconducting surface is provided. A pad dielectric layer having a thickness&#x2266;the second thickness is formed on the semiconductor surface including over the second regions, wherein the pad dielectric layer provides at least a portion of the second thickness for the second gate dielectric. A hard mask layer is formed on the semiconductor surface including over the second regions. A plurality of trench isolation regions are formed by etching through the pad dielectric layer and a portion of the semiconductor surface. The plurality of trench isolation regions are filled with a dielectric fill material to form trench isolation regions, and the hard mask layer is then removed. A patterned gate electrode layer is formed over the second gate dielectric, wherein said patterned gate electrode layer extends over a surface of at least one of the trench isolation regions. Fabrication of the MOS transistors in the first and second regions is then completed.

Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom

A protection structure ( &Prime;) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure ( &Prime;) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors ( ). In a pump transistors ( ), the gate electrode ( ) overlaps a portion of a well ( ) in which the drain ( ) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors ( ) are connected together and to the terminal (IN), while the gates of the transistors ( ) are connected together. The source of one transistor ( ) is connected to a guard ring ( ), of the same conductivity type as the substrate ( ) within which the channel region of the other transistors ( ) is disposed. An ESD event received at the terminal (IN) is thus coupled to the gate of the transistors ( ), causing conduction to the substrate ( ) via the guard ring ( ), and turning on a parasitic bipolar transistor at the other transistor ( ), safely conducting the ESD current. One alternative structure ( &prime;) includes a junction capacitor ( ) coupled between the terminal (IN) and the gates of the transistors ( ) to improve the coupling. Another alternative structure ( &Prime;) includes a clamping diode ( ) that also presents a parasitic bipolar transistor ( ) enhancing the current conducted to the substrate ( ).

Drain-extended MOS ESD protection structure

A transistor ( ) comprising a gate conductor ( ) and a gate insulator ( ) separating the gate conductor from a semiconductor material ( ) having a first conductivity type. The transistor further comprises a drain region ( ) having the first conductivity type. The transistor further comprises an angular implanted region ( ) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge ( ) underlying the gate conductor, and the transistor includes a source region ( ) formed at least in part within the angular implanted region. Finally, a transistor channel ( ) is defined between an edge ( ) of the source region proximate the gate conductor and the angular implanted region edge ( ) underlying the gate conductor.

Method of forming a metal oxide semiconductor transistor with self-aligned channel implant

An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate ( ) is formed over a CMOS n-well region ( ) and a CMOS p-well region ( ) in a silicon substrate ( ). Transistor source regions ( ), ( ) and drain regions ( ), ( ) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions ( ), ( ) serve as the drain extension regions of the transistor.

Higher voltage transistors for sub micron CMOS processes

A RESURF LDMOS transistor ( ) includes a RESURF region ( ) that is self-aligned to a LOCOS field oxide region ( ). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.

LDMOS device with self-aligned RESURF region and method of fabrication

A semiconductor device comprising a first transistor ( ) and a second transistor ( ), both formed in a semiconductor substrate ( ). The first transistor comprises a gate conductor ( ) and a gate insulator ( ) separating the gate conductor from a semiconductor material and defining a channel area ( ) in the semiconductor material opposite from the gate conductor. The first transistor further comprises a source (S ) comprising a first doped region ( ) of a first conductivity type and adjacent the channel area. Further, the first transistor comprises a drain (D ). The drain comprises a first well ( ) adjacent the channel area and having a first concentration of the first conductivity type and a first doped region portion and a second doped portion ( ). The first doped portion has a second concentration of the first conductivity type. The second concentration is greater than the first concentration and the first doped region portion has a common interface with the first well. The second doped region portion has the second concentration of the first conductivity type, wherein the second doped region portion has no common interface with the first well and is not adjacent the channel area. The second transistor ( ) comprises a second well ( ) formed using the same implant step as the first well and thereby having the first concentration of the first conductivity type. The second transistor further comprises a first source/drain ( ) and a second source/drain ( ), both comprising a second conductivity type complementary of the first conductivity type and formed within the second well.

Electrostatic discharge resistant extended drain metal oxide semiconductor transistor

LDMOS device with self-aligned resurf region and method of fabrication

A RESURF LDMOS transistor (,) has a drain region including a first region (,) and a deep drain buffer region (,) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.

Resurf LDMOS device with deep drain region

A temperature compensated photovoltaic module (20) comprised of a series of solar cells (22) having a thermally activated switch (24) connected in parallel with several of the cells (22). The photovoltaic module (20) is adapted to charge conventional batteries having a temperature coefficient (TC) differing from the temperature coefficient (TC) of the module (20). The calibration temperatures of the switches (24) are chosen whereby the colder the ambient temperature for the module (20), the more switches that are on and form a closed circuit to short the associated solar cells (22). By shorting some of the solar cells (22) as the ambient temperature decreases, the battery being charged by the module (20) is not excessively overcharged at lower temperatures. PV module (20) is an integrated solution that is reliable and inexpensive.

Temperature compensated photovoltaic array

The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications. The bipolar power transistors are more rugged and have higher power handling capabilities than DMOS devices. Thus the bipolar transistors can be used for any out-stage configuration, including low side, high side, half bridge and full bridge output circuits. The versatility of the present process flow allows the fabrication of MOSFET, BiMOS, BiCMOS, and bipolar technology either discretely or with high power or low power NPN or PNP devices.

Method of forming complementary bipolar and MOS transistor having power

An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

Complementary bipolar and MOS transistor having power and logic

An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.

Integrated circuit that combines multi-epitaxial power transistors with

A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Growing community of inventors

Plano, TX, United States of America

Dan M Mosher