Motorola Corporation

Dan L Burt

George F Anderson

David A Shumate

Richard F Taraci

Kevin A Lorenzen

John E Zavion

An improved process is described for depositing TiW/TiWN/TiW/Au metallization which provides superior adhesion properties, excellent barrier properties and which is suitable for use with metal line widths of the order of one micron or smaller. It is important in order to obtain these properties to ensure that the layer immediately underlying the gold layer by substantially pure TiW deposited in a nitrogen free sputtering atmosphere. To this end, the gas supply manifolds and deposition chamber are purged and the chamber evacuated following deposition of the TiW layer and prior to deposition of the TiWN layer underlying the gold layer. A final TiW layer is also conveniently placed on top of the gold layer to act as an etching mask.

Metallization process

Semiconductor devices with resistor regions, capable of operating at higher temperatures, and having improved bond pull strength are obtained by using a single layer (e.g. Ni--Cr) to act as a combined resistive layer and barrier layer. When placed in the contact windows between the semiconductor (e.g. Si) and the interconnect metallization, (e.g. Al) the Ni--Cr layer acts as a diffusion barrier to prevent interdiffusion of silicon and aluminum and contact alloying punch-through. When placed elsewhere on the device the Ni--Cr layer also serves as thin film resistor material. Wire bond pull strength is improved by placing an adhesion layer (e.g. polysilicon) beneath the portion of the resistive barrier layer underlying the bonding pads. The polysilicon layer rests on the insulator (e.g. SiO.sub.2) covering the semiconductor substrate.

Metallization means and method for high temperature applications

Semiconductor devices with resistor regions, capable of operating at higher temperatures, and having improved bond pull strength are obtained by using a single layer (e.g. Ni--Cr) to act as a combined resistive layer and barrier layer. When placed in the contact windows between the semiconductor (e.g. Si) and the interconnect metallization, (e.g. Al) and Ni--Cr layer acts as a diffusion barrier to prevent interdiffusion of silicon and aluminum and contact alloying punch-through. When placed elsewhere on the device the Ni--Cr layer also serves as thin film resistor material. Wire bond pull strength is improved by placing an adhesion layer (e.g. polysilicon) beneath the portion of the resistive barrier layer underlying the bonding pads. The polysilicon layer rests on the insulator (e.g. SiO.sub.2) covering the semiconductor substrate.

The present invention is directed to a method for forming a thin silicon dioxide deposited layer on a semiconductor structure. The silicon dioxide layer is formed in a hot wall furnace typically used for diffusions. A convenient temperature is selected from those which are suitable for decomposing the TEOS source of the silicon dioxide into its constituent parts out of which the silicon dioxide layer is formed. A vacuum is used to pull the TEOS gas through the diffusion tube. Care is exercised to assure that the flow of the TEOS material through the diffusion tube is kept at a constant rate. Prior to the first use of a new TEOS source bottle, the bottle is placed in a vacuum at least low enough to complete the boiling of impurities from the source material. This predeposition vacuum step is calculated to remove all the impurities contained in the source bottle and caused by the in situ decomposition of the source material during transit and storage. Whenever the source material is allowed to stand for any period of time; i.e., overnight or any number of hours, the predeposition vacuum step removes those impurities formed during the in situ decomposition of the source material since its last use. Wafers to be coated with a deposited oxide layer are placed in a furnace boat perpendicular to the flow of the source gas. In the preferred embodiment, the wafers are spaced 200 mils apart. While there is no indentified maximum distance between wafers at which the present invention ceases to operate successfully, undesirable results occur by placing adjacent wafers closer than 100 mils while acceptable results are achieved by placing the wafers 100-200 mils apart.

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Phoenix, AZ, United States of America

Dan L Burt