Advanced Micro Devices Corporation

Air Products and Chemicals, Inc.

Damon K DeBusk

Bruce L Pickelsimer

Andre Lagendijk

A method of manufacturing a silicon substrate which optimizes extrinsic gettering during semiconductor fabrication is provided in which phosphorous ions are diffused into the backside surface of a silicon substrate during wafer slice manufacture. Forming gettering sites at the backside surface prior to gate polysilicon deposition, extrinsic gettering is optimized. Initially, both the frontside and backside surfaces of a silicon substrate are subjected to dopant materials. Thereafter, at least one thin film is formed on both the frontside and backside surfaces. The thin films are then removed from the frontside surface along with a layer of the silicon substrate immediately below the frontside surface to a depth of about 10.0 .mu.m. The final polishing step of a typical silicon wafer manufacturing process removes a layer of silicon to a depth of about 10.0 .mu.m at the frontside surface of the silicon wafer, thus allowing the wafer slice material manufacturing method of the present invention to be easily be incorporated into a standard silicon wafer manufacturing process. It is estimated that at least 99 percent of the dopants introduced into the frontside surface are removed with the upper 10.0 .mu.m of silicon. The thin films formed on the backside surface of the silicon substrate remain, preventing outgassing of dopant impurities during subsequent thermal processing steps. A polysilicon thin film formed over the backside surface may also provide an additional source of extrinsic gettering.

Manufacturing method for wafer slice starting material to optimize

A method for the formation of active devices upon and within exposed surfaces of both sides of a silicon wafer is presented. A dual-sided silicon wafer is provided having a first surface and an opposed second surface prepared similarly to achieve surfaces suitable for fabricating semiconductor devices. The method advantageously integrates the ability to preform wafer processing operations on both exposed surfaces separately or simultaneously. Wafer processing operations are layering, patterning, doping, and heat treatment. The processing sequence is complete when a doped region and a patterened interconnect line electrically coupled thereto (i.e., minimal integrated circuits) are formed upon and within both surfaces of the dual-sided silicon wafer. A wafer handling system and processing station for dual-sided silicon wafers are described. In addition, a technique of applying a protective layer over one surface of a dual-sided silicon wafer is also described. Once a protective layer has been applied over one surface of a dual-sided silicon wafer, one or more wafer processing operations may be carried out upon the opposed surface using common wafer processing equipment without damaging the structures formed upon and within the surface covered with the protective layer. The protective layer may later be stripped away in order to gain access to the covered surface for further processing.

Method for forming active devices on and in exposed surfaces of both

A method and device is provided for removing a thin film from a wafer backside surface. The method and device advantageously removes the thin film without using photoresist masking material or the removal of photoresist material. The thin film at the wafer backside surface is removed without affecting any thin film material on the wafer front surface. As-such, the wafer backside surface is prepared for subsequent dopant ions used for extrinsic gettering of the backside surface. Alternatively, or in addition to dopants used for backside surface gettering, polysilicon can be deposited upon the exposed backside surface to enhance extrinsic gettering properties.

Method and device for removing a thin film from a wafer backside surface

A process for the use of organic chlorides having the general formula C.sub.x H.sub.y Cl.sub.y, C.sub.z Cl.sub.s, C.sub.r O.sub.u Cl.sub.2(r-u+1), C.sub.r O.sub.u Cl.sub.r-u+1 H.sub.r-u+1, wherein x=1-10, more preferably 1-6; y=x+1, x or x-1; z=1-10, more preferably 1-6; s=2(x+1, x or x-1), r=1-10, more preferably 2-4; u=1, 2 and up to r, as precursors for decomposition to chlorine and oxygen-containing reactive reagents for subsequent use for vapor cleaning of silicon, thermal oxidation of silicon in a range of 200.degree. C.-1200.degree. C., rapid thermal oxidation of silicon and silicon polishing or etching.

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Austin, TX, United States of America

Damon K DeBusk