Growing community of inventors

San Jose, CA, United States of America

Dale Kersten

Average Co-Inventor Count = 2.32

ph-index = 2

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 13

Dale KerstenShinichi Iketani (12 patents)Dale KerstenGeorge Dudnikov, Jr (3 patents)Dale KerstenDouglas Ward Thomas (2 patents)Dale KerstenSteve Iketani (0 patent)Dale KerstenDale Kersten (12 patents)Shinichi IketaniShinichi Iketani (26 patents)George Dudnikov, JrGeorge Dudnikov, Jr (14 patents)Douglas Ward ThomasDouglas Ward Thomas (5 patents)Steve IketaniSteve Iketani (0 patent)
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Inventor’s number of patents
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Strength of working relationships

Company Filing History:

1. Sanmina Corporation (12 from 96 patents)


12 patents:

1. 12150254 - Method of forming a laminate structure having a plated through-hole using a removable cover layer

2. 11765827 - Simultaneous and selective wide gap partitioning of via structures using plating resist

3. 11399439 - Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board

4. 11246226 - Laminate structures with hole plugs and methods of forming laminate structures with hole plugs

5. 10757819 - Method of forming a laminate structure having a plated through-hole using a removable cover layer

6. 10667390 - Simultaneous and selective wide gap partitioning of via structures using plating resist

7. 10362687 - Simultaneous and selective wide gap partitioning of via structures using plating resist

8. 10237983 - Method for forming hole plug

9. 10188001 - Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board

10. 10123432 - Simultaneous and selective wide gap partitioning of via structures using plating resist

11. 9781830 - Simultaneous and selective wide gap partitioning of via structures using plating resist

12. 9781844 - Simultaneous and selective wide gap partitioning of via structures using plating resist

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as of
12/6/2025
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