Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kabushiki Kaisha Toshbia

Daisuke Matsushita

Shosuke Fujii

Yasushi Nakasaki

Akira Takashima

Yuichiro Mitani

Koichi Kato

Koichi Muraoka

Hidenori Miyagawa

Tsunehiro Ino

Yuuichiro Mitani

Kiwamu Sakuma

Chika Tanaka

Kensuke Ota

Masumi Saitoh

Naoki Yasuda

Reika Ichihara

Jun Fujiki

Masao Shingu

Yoshio Ozawa

Takayuki Ishikawa

Yukie Nishikawa

Yoshifumi Nishi

Hideki Satake

Noburu Fukushima

Isao Kamioka

Misako Morota

Izumi Hirano

Ryuji Ooba

Yoshihisa Iwata

Takeshi Imamura

Takeshi Yamaguchi

Tsutomu Tezuka

Seiji Inumiya

Nobutoshi Aoki

Yuuichi Kamimuta

Atsushi Murakoshi

Hiroki Tanaka

Kazuhiro Eguchi

Takashi Shimizu

Toshihide Ito

Kenichiro Toratani

Yusuke Arayashiki

Masamichi Suzuki

Masahiro Koike

Takashi Yamauchi

Ryuji Ohba

Mariko Takayanagi

Takamitsu Ishihara

Shigeto Fukatsu

Kouichi Muraoka

Toshifumi Irisawa

Masayasu Miyata

Hideki Inokuma

Tomoya Kawai

Riichiro Takaishi

Takashi Haimoto

A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.

Nonvolatile semiconductor memory device having electron scattering and electron accumulation capacities in charge accumulation layer

According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Resistance-change memory operating with read pulses of opposite polarity

According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a second conductivity type in the semiconductor region; a gate electrode above a first part of the semiconductor region between the first region and the second region; a gate insulating layer between the first part and the gate electrode; a third region having the first conductivity type below the second region; and a fourth region across the second region and the third region and including a first impurity.

Semiconductor device and semiconductor memory device

A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.

It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Semiconductor device and method for manufacturing the same

A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.

Semiconductor device and dielectric film including a fluorite-type crystal

A semiconductor device of an embodiment includes an oxide semiconductor layer including a first region, a second region and the third region provided between the first region and the second region. The oxide semiconductor layer contains indium (In), gallium (Ga), and zinc (Zn). The first and second regions have thinner film thickness and lower indium (In) concentration than the third region. An insulating film is provided on the third region, and an electrode is provided on the insulating film. A first conductive layer is provided under the first region and electrically connected with the first region. A second conductive layer is provided under the second region and electrically connected with the second region.

Semiconductor device and method of manufacturing the same

According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc2.

Insulator and memory device

Resistance-change memory having on-state, off-state, and intermediate state

According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.

Nonvolatile variable resistance element

A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.

Nonvolatile semiconductor memory

A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and memory cells at intersections of the first and second wiring lines, the memory cells being stacked perpendicularly to a substrate, each memory cell comprising a variable resistance element; a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines; a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines; and a peripheral circuit layer on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells. The first select transistor layer is provided below the memory cell array perpendicularly to the substrate. The second select transistor layer is provided above the memory cell array perpendicularly to the substrate.

An element according to an embodiment can transit between at least two states including a low-resistance state and a high-resistance state. The element comprises a first electrode, a second electrode, a first layer and a second layer. The first electrode includes metal elements. The first layer is located between the first electrode and the second electrode while contacting with the first electrode. The second layer is located between the first layer and the second electrode. At the low-resistance state, a density of the metal elements in the first layer is higher than that of the metal elements in the second layer. The density of the metal elements in the first layer at the low-resistance state is higher than that of the metal elements in the first layer at the high-resistance state. A relative permittivity of the second layer is higher than a relative permittivity of the first layer.

Variable resistive element, storage device and driving method thereof

Growing community of inventors

Fujisawa, Japan

Daisuke Matsushita