Fujitsu Corporation

Fujitsu Vlsi Limited

Daisuke Komada

Kenichi Watanabe

Fumihiko Shimpuku

Satoru Mihara

A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

Semiconductor device with dual damascene wiring

The surface of an insulating film made of silicon-containing insulating material is covered with a mask pattern. The insulating film is dry-etched by using the mask pattern as a mask and etching gas which contains C F gas and C F gas (wherein x and y are an integer and satisfy x&gE;5 and y&lE;(2x&minus;1). In the dry-etching process, a sufficient etching selection ratio can be obtained between a layer to be etched and an underlying etching stopper film.

Manufacture method for semiconductor device having silicon-containing insulating film

A semiconductor device manufacturing method having a multi-layered wiring structure comprises the steps of forming an insulating film over a semiconductor substrate, coating resist on the insulating film, forming a wiring pattern window in the resist, forming a wiring recess by etching the insulating film via the window, removing the resist, removing a reaction product existing on the insulating film by exposing the insulating film to a plasma atmosphere using an inactive gas, and burying a metal film into the wiring recess to form a wiring.

Semiconductor device manufacturing method

A method for fabricating a semiconductor device including a conductive pattern having a first layer including Ti and a second layer including W is presented. The method includes the steps of patterning the conductive pattern by a dry etching and exposing the conductive pattern after the step of the patterning to a plasma containing O, thereby removing the remaining Cl which induces an aftercorrosion problem of the conductive pattern containing the Ti.

Method for manufacturing a semiconductor device

A semiconductor integrated circuit device, having: a plurality of semiconductor elements formed in a central circuit area of a semiconductor chip; a plurality of insulating layers formed on the semiconductor chip; cavities for forming wiring layers of a multi-layer structure, each of the cavities in each wiring layer having a via hole and a wiring pattern trench; wiring layers of the multi-layer structure including a via conductor filled in the via hole and a wiring pattern filled in the wiring pattern trench; moisture-proof ring trenches of a multi-layer structure corresponding to the cavities for forming the wiring layers of the multi-layer structure, the moisture-proof ring trenches surrounding the circuit area in a loop-shape and formed through the insulating layers, a width of each of the moisture-proof ring trenches corresponding to a corresponding one or ones of the via holes being set smaller than a minimum diameter of the via holes; and a conductive moisture-proof ring filled in a corresponding one of the moisture-proof ring trenches. In etching via holes and a moisture-proof ring trench, it is possible to suppress the stopper film in the moisture-proof ring trench from being thinned and to minimize damages to the underlying wiring layer.

Semiconductor integrated circuit device with moisture-proof ring and its manufacture method

A method for ashing a resist on a wafer in a plasma reaction chamber comprises the steps of flowing a non-activated oxygen containing gas into the plasma reaction chamber immediately before loading the wafer to the plasma reaction chamber, and then carrying out a plasma ashing of the resist. In one of the preferred embodiments, after the reaction chamber was exposed to the atmosphere and then evacuated to vacuum, a mixed gas of oxygen (90% in volume) and water vapor (10% in volume) was flown into the reaction chamber with 1000 seem and 1 Torr for 5 min. and subsequently the ashing was carried out. The method prevents the ashing rate from decreasing with ashing time.

Growing community of inventors

Kasugai, Japan

Daisuke Komada