Fujitsu Corporation

Daisuke Fukuda

Izumi Nitta

Tetsuyoshi Shiota

Shunichi Watanabe

Satoko Iwakura

Masaru Todoriki

A machine learning method includes acquiring data including attendance records of employees and information indicating which employee has taken a leave of absence from work, in response to determining that a first employee of the employees has not taken a leave of absence in accordance with the data, generating a first tensor on a basis of an attendance record of the first employee and parameters associated with elements included in the attendance record, in response to determining that a second employee of the employees has taken a leave of absence in accordance with the data, modifying the parameters, and generating a second tensor on a basis of an attendance record of the second employee and the modified parameters, and generating a model by machine learning based on the first tensor and the second tensor.

Machine learning method

A learning device receives, for each target, learning data that represents the source of generation of a tensor including a plurality of elements which multi-dimensionally represent the features of the target over a period of time set in advance. When the target satisfies a condition set in advance, the learning device identifies the period of time corresponding to the condition in the learning data. Subsequently, the learning device generates a weighted tensor corresponding to the learning data that is at least either before or after the concerned period of time.

Computer-readable recording medium and learning data generation method

A design supporting device includes a calculator that calculates an estimated value of a width, shifted by etching, of a wiring arranged in each of partial regions formed by dividing a layout region of a circuit to be designed on basis of a density of the wiring of the partial region, a length of a circumference of the wiring and a distance between the partial region and another partial region affecting the partial region, and uses the calculated estimated value to recalculate the density of the wiring of the partial regions, and a changer that changes the density of the wiring on basis of relationships between a recalculated density of the wiring and a preset threshold for the density.

Supporting device, design support method and computer-readable recording medium

A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.

Polishing estimation/evaluation device, overpolishing condition calculation device, and computer-readable non-transitory medium thereof

A dummy-mesh-information creating unit separates a group of dummy metal blocks that are arranged in a pattern regularly staggered with respect to a direction of a wire object into meshes so that each mesh has the same layout of dummy metal blocks. An overlap determining unit determines whether a dummy metal block within a dummy mesh overlaps with the wire object. A dummy-information calculating unit calculates dummy information after any dummy metal block that is determined to be overlapped with the wire object is removed. An information integrating unit integrates the dummy information with information about the wire object, thereby generating a dummy-fill circuit layout. An evaluating unit evaluates whether the dummy-fill circuit layout satisfies the design criteria.

Dummy-metal-layout evaluating device and dummy-metal-layout evaluating method

A computer readable recording medium stores therein a plated film thickness calculating program for a semiconductor integrated circuit producing process in which a plating treatment, a polishing treatment and an over-polishing treatment are performed. The plated film thickness calculating program performing a process includes simulating the plating treatment of plating the surface of the substrate for a given thickness of the conductor; calculating a thickness of the conductor to be removed by the polishing treatment until at least a part of the plateaus appears; calculating a maximum thickness of the conductor to be remained on any part of the plateaus after performing the polishing treatment; and repeating the simulating, the thickness calculation and the maximum thickness calculation by changing the given thickness until a minimum of the given thickness is determined in which the maximum thickness of the remaining conductor becomes less than a predetermined level.

Plated film thickness calculating method and plated film thickness calculating device

A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and the minimum edge length of the partial regions are limited. Thus, the respective wiring densities and respective edge lengths of the partial regions are constrained within a constant range and irregularities in the substrate surface after polishing can be suppressed.

Layout design apparatus, layout design method, and computer product

A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas.

Semiconductor integrated circuit manufacturing process evaluation method

A film thickness predicting apparatus compares a measurement value of a copper plating formed on wiring grooves of various patterns measured using a TEG and a film thickness of the copper plating calculated based on a plating model and a condition file. The film thickness predicting apparatus then delivers optimal plating model from the comparison result and calculates the film thickness of the copper plating formed on a substrate surface to be designed using the optimal plating model. The film thickness predicting apparatus enables to conduct a highly accurate film thickness predicting simulation.

Film thickness predicting program, recording medium, film thickness predicting apparatus, and film thickness predicting method

An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs, based on the clock tree, a plurality of groups each of which includes a part of elements of same skew; an analyzing unit that performs an analysis of a timing of an inter-group path between two of the groups; and an output unit that outputs a result of the analysis.

Method and apparatus for constructing and optimizing a skew of a clock tree

A polishing-condition predicting apparatus determines optimum parameters to be substituted into various function models by performing calibration by use of a TEG. A polishing condition enabling polishing of a thin film formed on a substrate to be designed so as to obtain a desirable height of the thin film and a desirable depth of a groove is predicted by simulation using the determined optimum parameters.

Growing community of inventors

Kawasaki, Japan

Daisuke Fukuda