Sandisk Technologies Inc.

Sandisk Technology LLC

Dai Iwata

Hiroyuki Ogawa

Kazutaka Yoshizawa

Hiroshi Nakatsuji

Mitsuhiro Togo

Eiichi Fujikura

Hokuto Kodate

Yasuaki Yonemochi

Hiroyuki Kinoshita

Murshed Chowdhury

Jin Liu

Kota Funayama

Kiyokazu Shishido

Yusuke Yoshida

Tadashi Nakamura

Matthias Baenninger

Marika Gunji-Yoneoka

Kazuya Tokunaga

Jiyin Xu

Takeshi Kawamura

Jun Akaiwa

Masahiro Yaegashi

Yasushi Ishii

Akihiro Yuu

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Transistor circuits including fringeless transistors and method of making the same

A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.

At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.

Gate material-based capacitor and resistor structures and methods of forming the same

A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.

CMOS devices containing asymmetric contact via structures

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same

A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.

Select gates with central open areas

A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes an opening through an interpoly dielectric layer, floating gate layer, and tunnel dielectric layer, the opening separated from the substrate surface by a select gate dielectric on the substrate surface, the opening filled by a control gate layer.

Select gates with select gate dielectric first

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Dai Iwata