Hitachi, Ltd.

Dai Hisamoto

Masahiro Moniwa

Toru Kaga

Eiji Takeda

Atsushi Hiraiwa

ShinIchiro Kimura

Haruhiko Tanaka

Shoji Shukuri

Kozo Katayama

Shinichiro Kimura

Shinichi Minami

Kazuhiko Sagara

Tsuyoshi Kachi

It is an object of the present invention to provides a field effect transistor with extremely low leakage current. It is another object of the invention to provide a semiconductor memory device having an excellent information holding characteristic. It is a further object of the invention to provide a method for manufacturing in a simple manner a novel field effect transistor or semiconductor memory device with extremely low leakage current. According to a typical basic configuration of the present invention, a thin insulating film is inserted in a vertically disposed Schottky junction to form source and drain electrodes and a tunnel of the insulating film in the junction is controlled by a gate electrode. The gate electrode is disposed on each of both sides of a vertical channel, permitting a field effect to be exerted effectively on the junction, whereby a junction leakage in an OFF state can be made extremely low.

Vertical semiconductor device with tunnel insulator in current path controlled by gate electrode

A semiconductor integrated circuit device wherein plural field effect transistors having different threshold values are integrated on one chip by forming plural gate electrodes of silicon-germanium mixed crystals having different germanium contents. By varying the germanium content of the gate electrode material, a work function with respect to the channel region can be varied, so a semiconductor integrated circuit device wherein plural field effect transistors having different threshold voltage values are integrated on one chip can be manufactured.

Semiconductor integrated circuit device and method of manufacturing thereof

A semiconductor memory device is constituted by forming two types of insulation films on the channel of an MOS transistor on which a vertical type another MOS transistor using the control gate of the MOS transistor as a substrate is stacked. Thus, a non-volatile semiconductor memory device small in size, having high reliability, high density, excellent fatigue and a random access function can be provided.

Semiconductor memory device

Short and long sides of each of capacitors held by a semiconductor memory device are respectively made shorter and longer so that the capacitors are laid over memory cell regions adjacent to each other. Thus, large capacity type capacitors whose circumferential length increases and total capacitor area greatly increases can be obtained without so increasing plane areas of the capacitors.

Semiconductor memory device and method of manufacturing same

A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

Method of manufacturing a semiconductor device having silicon islands

A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.

Capacitive memory having a PN junction writing and tunneling through an

An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Method for manufacturing a semiconductor device and a semiconductor

A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

Growing community of inventors

Kokubunji, Japan

Dai Hisamoto