Vanguard International Semiconductor Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Other

Dahcheng Lin

Hsi-Chuan Chen

Jung-Ho Chang

Kuo-Shu Tseng

Chih-Hsing Yu

Min-hwa Chi

Chingfu Lin

A method for fabricating an MIM capacitor on a substrate. A region of the substrate is dedicated for use as an electrode area of the MIM capacitor. The electrode area of the MIM capacitor may be increased by utilizing at least one spacer formed on an associated planar metal surface, wherein the planar metal surface is formed upon the substrate. An increase in a gain factor of the electrode area is thus dependent upon an associated spacer height and particular number of islands or vias. A roughened surface is thus created for use as a roughened electrode for subsequent capacitor processes. Fabricating spacers made of conducting or non-conducting materials on the associated planar metal surface can create such an electrode. The MIM capacitor formed thereof can be utilized in mixed-signal and RF applications and is fully compatible with COMS logic fabrication processes.

Low temperature MIM capacitor for mixed-signal/RF applications

A method of planarizing the peripheral circuit region of a DRAM. A first oxide layer and a silicon nitride layer are sequentially formed over a substrate. A plurality of polysilicon plugs are formed within the crown-shaped capacitor region of the DRAM. A patterned second oxide layer is formed over the silicon nitride layer. A conformal doped amorphous silicon layer is formed over the exposed surface of the crown-shaped capacitor region and the peripheral circuit region of the DRAM. A photoresist layer is formed over the crown-shaped region and then a nitrogen implant is carried out to form a silicon oxy-nitride barrier layer. A chemical-mechanical polishing is carried out to separate the various lower electrodes. The photoresist layer and the second oxide layer within the crown-shaped capacitor region are removed. Hemispherical silicon grains are grown on the exposed surface of the doped amorphous silicon layer. A dielectric layer and an upper electrode layer are sequentially formed over the hemispherical silicon grains on the doped amorphous silicon layer.

Method of planarizing peripheral circuit region of a DRAM

A method of manufacturing a crown-shaped DRAM capacitor. A silicon oxide layer and a silicon nitride layer are sequentially formed over a substrate. A conductive plug passing through the silicon oxide layer and the silicon nitride layer is formed. A first and a second dielectric layer are sequentially formed over the silicon nitride layer and the conductive plug. A first opening that exposes the conductive plug and a portion of the silicon nitride layer surrounding the plug is formed in the second and the first dielectric layer. A doped amorphous silicon layer conformal to the substrate profile is formed. The doped amorphous silicon layer above the second dielectric layer is removed. The second dielectric layer is next removed, and then hemispherical silicon grains (HSGs) are grown over the exposed surface of the doped amorphous silicon layer. The first dielectric layer is removed, and finally a third dielectric layer and a conductive layer are sequentially formed over the substrate.

Method of manufacturing crown-shaped DRAM capacitor

A method for manufacturing a bottom storage node of a stack capacitor on a substrate is disclosed. The method comprises the steps of: (1) forming a first dielectric layer onto said substrate; (2) forming a nitride layer onto said first dielectric layer; (3) patterning and etching said first dielectric layer and said nitride layer until said substrate is reached, to form a contact opening; (4) forming a first conducting layer into said contact opening and atop said nitride layer; (5) removing a portion of said first conducting layer atop said first dielectric layer to form a plug in said contact opening; (6) forming a second dielectric layer atop said nitride layer and said plug; (7) patterning and etching said second dielectric layer to form a trench above said plug; (8) forming an amorphous polysilicon layer into said trench and atop said second dielectric layer; (9) removing a portion of said amorphous polysilicon layer atop said second dielectric layer; (10) removing remaining portion of said second dielectric layer; and (11) forming an HSG polysilicon layer atop said amorphous polysilicon layer.

Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon

A method of reading a 2-bit memory cell having a drain, a source, a control gate, and a floating gate is disclosed. First, a voltage is applied to the source and drain to generate a gate induced drain leakage (GIDL) current. Next, a measurement is taken of a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.

Method for reading 2-bit ETOX cells using gate induced drain leakage current

A method for forming a contact plug. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening that exposes a thin layer of native oxide. A first and a second conformal doped polysilicon layer are formed over the opening. The first doped polysilicon layer has a dopant concentration greater than that of the second doped polysilicon layer. A third doped polysilicon layer that also fills the opening is formed over second doped polysilicon layer. Dopant concentration of the third doped polysilicon layer is smaller than the second doped polysilicon layer. Last, the first, the second and the third doped polysilicon layer are annealed.

Method for forming contact plug

A method of fabricating a twin-tub capacitor is described in which a dielectric layer is defined to form multiple column structures, followed by forming a conductive layer over the column structures. The conductive layer on the top surface of the column structures are removed by chemical mechanical polishing to isolate each capacitor. The column structures are further removed to form a twin-tub capacitor.

Fabrication method of a twin-tub capacitor

A method of creating a DRAM capacitor structure, featuring a crown shaped storage node structure, has been developed. The crown shaped storage node structure, features the formation of an hemispherical grain, (HSG), silicon layer, only on a top portion of the structure, with the bottom portion of the crown shaped storage node structure, featuring non - HSG, or smooth surfaces. This configuration is achieved via creation of a capacitor opening, in a doped oxide - undoped oxide, composite insulator layer, used as the shape for subsequent formation of an amorphous silicon crown shaped structure. Selective removal of the overlying doped oxide layer, allows selective formation of an HSG silicon layer, only on the exposed top portion of the amorphous silicon crown shaped structure. Subsequent removal of the undoped oxide layer, exposes a bottom portion of the amorphous silicon crown shaped structure, featuring non - HSG silicon surfaces, allowing easier formation of a capacitor dielectric layer, specifically at the bottom corner of the crown shaped storage node structure.

Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure

A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG silicon layer, on a doped amorphous silicon, storage node shape, with the HSG silicon layer supplying increased surface area, and thus increased capacitance, for the DRAM capacitor. A doped polysilicon layer, selectively deposited on the underlying HSG silicon layer, supplies additional dopant to the HSG silicon layer, residing on the doped amorphous silicon, storage node shape, thus minimizing a capacitance depletion phenomena, that can be present with lightly doped storage node structures.

Method to decrease capacitance depletion, for a DRAM capacitor, via

A method of forming hemispherical grain (HSG) silicon is disclosed. The method comprises the steps of: forming a doped amorphous silicon layer on a substrate; seeding and annealing the amorphous silicon layer until HSG silicon is formed; enlarging the HSG silicon grains during the annealing stage; and performing a chemical dry etch on the HSG silicon to remove an undoped silicon layer from the surface of the HSG silicon.

Method for reducing capacitance depletion during hemispherical grain

A method for insitu forming a SiN layer and an overlying Silicon oxynitride layer in one chamber. A substrate is loaded into a chamber. The substrate has thereover a polysilicon layer and a overlying metal layer. In a first in-situ step, a nitride layer is deposited using a LPCVD process over the substrate. The nitride layer is preferably formed at a temperature between 650 and 800.degree. C. and flowing SiH.sub.2 Cl.sub.2 and NH.sub.3. In a second in-situ step, an oxynitride layer is deposited over the nitride layer. The oxynitride layer acts as a bottom anti-reflective coating (BARC). The oxynitride (SiON) layer can be formed by a LPCVD process. Second, the LPCVD oxynitride can be formed a temperature between 600 and 800.degree. C. with a SiH.sub.4 flow and a N.sub.2 O flow. The substrate is removed from the chamber. A photoresist layer is formed over the oxynitride layer. The photoresist layer is exposed using the oxynitride layer as a bottom anti-reflective coating (BARC). The photoresist layer is developed. The oxynitride layer, the nitride layer, the metal layer and the polysilicon layer are etched to form a gate structure. The gate structure has sidewalls. Spacers are formed on the sidewalls of the gate structure. An ILD layer is formed over the gate structure. A contact hole is etched through the ILD layer using the gate structures and spacers as a mask to expose the substrate to form a self aligned contact (SAC) opening.

In-situ nitride and oxynitride deposition process in the same chamber

A process for creating a DRAM capacitor structure, comprised of a storage node electrode, featuring an HSG silicon layer, on the surface of the storage node electrode, used to increase capacitor surface area, has been developed. The process features the use of a UHV system, allowing: a pre-clean procedure; an HSG seeding procedure; an anneal procedure used to create an HSG silicon layer; and a silicon nitride deposition; all to be performed in situ, without exposure to air, thus removing, and avoiding, unwanted native oxide layers. This invention allows a nitride--oxide, capacitor dielectric layer, to be formed in situ, in the UHV system, on an underlying storage node electrode structure, which in turn experienced in situ procedures, in the UHV system, resulting in HSG silicon layer, formed after an in situ, pre-clean, an HSG silicon seeding procedure, and an anneal procedure.

In situ, one step, formation of selective hemispherical grain silicon

A method of forming a capacitor. A substrate comprises a cell array area and a peripheral area. A dielectric layer is formed on the substrate. The covering layer is formed on the dielectric layer. The contact electrode is formed through the dielectric layer and the covering layer. The first oxide layer is formed over the substrate. A portion of the first oxide layer is removed to form an opening, which exposes the contact electrode. A conformal preserve layer is formed over the substrate. A second oxide layer is formed over the substrate. A portion of the second oxide layer in the cell array area is removed to form an opening, which exposes the contact electrode. A conformal first conductive layer is formed over the substrate to cover the second oxide layer and the opening. A third oxide layer is formed over the substrate to cover the first conductive layer and fill the opening. A planarization step is performed to remove the third oxide layer, the first conductive layer, and the second oxide layer until the preserve layer in the peripheral area is exposed. The third oxide layer and the second oxide layer in the cell array area are removed to expose conductive layer. A selective hemispherical grained silicon layer and a dielectric film are formed in sequence over the exposed conductive layer. A second conductive layer is formed over the substrate to fill the opening.

Method of fabricating capacitor capable of maintaining the height of the

An improved and new process for fabricating planarized isolation trenches, wherein sharp corners at the top periphery of the trench are eliminated and erosion of insulating material at the edges of isolation trenches is suppressed, has been developed. The process uses a two layer mask to etch the isolation trench, followed by an isotropic etch to recess the first layer of the mask. An oxide liner is formed in the trench and across the exposed edge of the trench resulting in rounding the corners of the trench. Then, a second isotropic etch is used to recess the edge of the second mask layer, so that its opening now is beyond the edge of the trench. An oxide layer is conformally deposited over all exposed surfaces and fills the trench. After CMP to planarize the oxide layer, the remaining oxide fills the trench and, also, extends a small distance beyond the edge of the trench and serves to protect edge of the trench during subsequent etching.

Process for recess-free planarization of shallow trench isolation

A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer. Patterning, or CMP, of the doped HSG silicon layer, and of the heavily doped amorphous silicon layer, results in the creation of a storage node electrode. The use of the composite buffer layer allows the growth of an undoped HSG silicon layer to be achieved, thus maximizing uniformity and HSG silicon roughness, while the anneal cycle, applied to the undoped HSG silicon layer, results in the attainment of the doped HSG silicon layer, offering reduced capacitance depletion compared to undoped HSG silicon counterparts.

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Hsinchu, Taiwan

Dahcheng Lin