Taiwan Semiconductor Manufacturing Comp. Ltd.

Dah Lin

Yeur-Luen Tu

Min-hwa Chi

Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450&deg; C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity. After the capacitor cavity is formed by either method, the sidewall of the deep cavity is coated sequentially with a conformal conducting film as the bottom electrode and a high-k dielectric, and then filled with a conducting material to form the top electrode.

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Hsinchu, Taiwan

Dah Lin