International Business Machines Corporation

Novellus Systems Incorporated

Samsung Electronics Co., Ltd.

Daewon Yang

Richard Anthony Conti

Huilong Zhu

Yun-Yu Wang

Kangguo Cheng

Keith Kwong Hon Wong

Kwong Hon Wong

Anita Madan

Nancy R Klymko

Roy H Tilghman

Michael C Smits

Ronald P Bourque

Richard Stephan Wise

Michael P Belyansky

Yanfeng Wang

Jae-Eun Park

Woo-Hyeong Lee

Pavel Smetana

Tai-chi Su

Junjung Kim

Chih-Chao Yang

Lawrence Alfred Clevenger

Oleg Gluschenkov

Xiangdong Chen

John Anthony Fitzsimmons

Brian Joseph Greene

Unoh Kwon

Rajasekhar Venigalla

David Lee Rath

Naftali Eliahu Lustig

Byeong Yeol Kim

Huajie Chen

Kaushik Chanda

Michael F Lofaro

Rishikesh Krishnan

Sunfei Fang

Michael Vincent Aquilino

Christopher D Sheraw

Andreas Knorr

Ja-Hum Ku

Kenneth M Davis

Christopher V Baiocco

Thomas F Houghton

Deleep R Nair

Jeffery Burton Maxson

Ann H McDonald

Patricia Argandona

Massud A Aminpur

Gregory DiBello

Chih-Chao Ibm United Kingdom Limited Yang

A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.

CMOS structures and methods for improving yield

Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

Method and apparatus for angular high density plasma chemical vapor deposition

A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an 'electron filter' that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.

A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600&#xb0; C. or less.

Shallow trench isolation for device including deep trench capacitors

Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Method for controlling structure height

A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.

Semiconductor structure

A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Structure and method to fabricate MOSFET with short gate

Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cmand 5.0 W/cm; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Compressive nitride film and method of manufacturing thereof

A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 &#x212b;.

Method of forming nitride films with high compressive stress for improved PFET device performance

A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage.

Structure and method for reducing threshold voltage variation

A stress nitride structure is formed on an integrated circuit field effect transistor by high density plasma (HDP) depositing a first stress nitride layer on the integrated circuit field effect transistor and then plasma enhanced chemical vapor depositing (PECVD) a second stress nitride layer on the first stress nitride layer. The first stress nitride layer is non-conformal and the second stress nitride layer is conformal. Related structures also are described.

HDP/PECVD methods of fabricating stress nitride structures for field effect transistors

An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.

Method of forming an interconnect including a dielectric cap having a tensile stress

A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.

CMOS structures and methods using self-aligned dual stressed layers

A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

Dual layer stress liner for MOSFETS

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Hopewell Junction, NY, United States of America

Daewon Yang