Samsung Electronics Co., Ltd.

Daeseok Byeon

Chanho Kim

Pansuk Kwak

Jooyong Park

Taehyo Kim

Chiweon Yoon

Taehong Kwon

Donghun Kwak

Dongku Kang

Youngmin Jo

Sunghoon Kim

Bongsoon Lim

Hongsoo Jeon

Kyunghwa Yun

Seungyeon Kim

Hyunsurk Eric Ryu

YongSung Cho

Joo-Yong Park

Changyeon Yu

Jun Jin Kong

Sang-Wan Nam

Hong Rak Son

Minsu Kim

Seungwon Lee

Jisu Kim

Eun Chu Oh

Ji-sang Lee

Sangwan Nam

Yonghyuk Choi

Jaeduk Yu

Pilsang Yoon

Sangwon Park

Tongsung Kim

Taeyun Lee

Youngsun Min

Gyosoo Choo

Changbum Kim

Taehyun Song

Dongsup Jin

Dongjin Shin

Jinbae Bang

Jung-Hwan Lee

Sanghoon Ahn

Yoon-Hee Choi

Kisung Kim

Bong-Kil Jung

Ahreum Kim

Sujeong Kim

Hee-Woong Kang

Ju Seok Lee

Chang-Bum Kim

Jeeyong Kim

Inho Kang

Hyunkook Park

Myoung-Won Yoon

Beakhyung Cho

Yeongtaek Lee

Taemin Ok

Min-Hwi Kim

Byunggil Jeon

Inmo Kim

Jaehue Shin

Takuya Futatsuyama

Minjeong Heo

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.

Memory device including page buffer circuit

A memory device includes a memory cell array, and a plurality of page buffer units, the page buffer units each including a sensing node, a data transfer node, a first transistor precharging the data transfer node, a second transistor connecting the sensing node to the data transfer node, a sensing latch connected to the data transfer node, a third transistor changing a data value of the sensing latch, and a fourth transistor connecting the third transistor to the data transfer node, wherein, during a sensing operation, in a first time period, the sensing node is precharged based on a first path through the first transistor, the data transfer node, and the fourth transistor, and in a second time period, a voltage of the sensing node is set to a threshold voltage according to a second path through the fourth transistor, the data transfer node, and the third transistor.

Memory device including page buffer circuit and SSD including the memory device, and method of using the same

Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

Non-volatile memory device with high voltage region and low voltage region

Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.

Memory device having asymmetric page buffer array architecture

A memory device includes a memory cell array connected to a plurality of word lines, a clock generator configured to generate a clock signal, a charge pump circuit configured to generate a voltage to be provided to the plurality of word lines, based on the clock signal, a row decoder configured to provide the voltage to a selected memory block, a current generation circuit connected in parallel to a word line path through which the voltage is provided from the charge pump circuit to the row decoder and configured to generate a current flowing through the word line path for a reference time, and a defect detection circuit configured to detect a defect on the word line path by comparing a first count value of the clock signal counted before the reference time with a second count value of the clock signal counted after the reference time.

Memory device detecting defect of word line path and operating method thereof

In some embodiments, a semiconductor memory device includes a peripheral circuit structure, and a first and a second cell array structure. The peripheral circuit structure includes a circuit board, a peripheral circuit on the circuit board, a first insulating layer, and a plurality of first bonding pads on the first insulating layer. The first cell array structure includes a first memory cell array, a first conductive plate structure, a second insulating layer, and pluralities of second and third bonding pads on the second insulating layer. The second cell array structure includes a second memory cell array, a second conductive plate structure, a third insulating layer, and a plurality of fourth bonding pads on the third insulating layer. The first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure.

Semiconductor memory devices and method of manufacturing the same

A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Memory device including pass transistor circuit

A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device

A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

Vertical semiconductor device

An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

Integrated circuit including power gating circuit

An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

Integrated circuit device

Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

Memory device having physical unclonable function and memory system including the memory device

Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

Three-dimensional semiconductor devices

Flash memory device includes: first pads to be bonded to external semiconductor chip, to receive at least one of command, address and control signals; second pads to be bonded to external semiconductor chip; memory cell array including memory cells; a row decoder block connected to memory cell array through word lines, to select one of word lines based on address provided to row decoder block; a buffer block to store command and address and provide address to row decoder block; a page buffer block connected to memory cell array through bit lines, connected to second pads through data lines without passing through buffer block, and configured to exchange data signals with external semiconductor chip through data lines and second pads; and a control logic block configured to receive command from buffer block, to receive control signals from external semiconductor chip, and to control row decoder block and page buffer block.

Flash memory device configured to be bonded to external semiconductor chip and computing device including flash memory device coupled to neural processor chip

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Seongnam-si, South Korea

Daeseok Byeon