Qualcomm Incorporated

International Business Machines Corporation

Daeik Daniel Kim

Jonghae Kim

Changhan Hobie Yun

Mario Francisco Velez

Chengjie Zuo

David Francis Berdy

Je-Hsiung Lan

Robert Paul Mikulka

Niranjan Sunil Mudakatte

Moon Jung Kim

Matthew Michael Nowak

Choongyeun Cho

Karl J Duvalsaint

Moon Ju Kim

Harm Peter Hofstee

James Randal Moulic

Xiangdong Zhang

Young Kyu Song

Xiaonan Zhang

Yunfei Ma

Manuel Aldrete

Ryan David Lane

Babak Nejati

Jie Fu

Jean-Olivier Plouchart

Puay Hoe See

Robert E Trzcinski

Bonhoon Koo

Husnu Ahmet Masaracioglu

Chung-Hsun Lin

Shiqun Gu

Chandrasekharan Kothandaraman

Ravindra Vaman Shenoy

Chin-Kwan Kim

John Matthew Safran

Jon Lasiter

Donald William Kidwell, Jr

Kwan-Yu Lai

Jitae Kim

Xia Li

Bin Yang

Jung Pill Kim

Taehyun Kim

Sungryul Kim

Sang-June Park

Richard C Ferri

Dan Peter Dumarot

Jong-Hoon Lee

Uei-Ming Jow

Jung Ho Yoon

Daniel Wayne Perry

Rick Allen Wilcox

Eugene B Risi

Shu Zhang

Ryan Scott C Spring

Elmer K Corbin

Je-Hsiung Jeffrey Lan

Elmer Kenneth Corbin

Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

High performance inductors

A laminate substrate inductor reduces insertion loss and improves isolation while reducing the area for integrating the laminate substrate inductor. The laminate substrate includes a spiral trace. The laminate substrate also includes a first capture pad at a first end of the spiral trace. The first end is located at a corner of the spiral trace. The first capture pad is substantially within a bounding box of the spiral trace. At least a portion of the first capture pad and an outer edge of the spiral trace have a same distance from a ground.

Inductor with embraced corner capture pad

A multi-layer spiral inductive array includes a first multi-layer spiral inductor with a second layer matching a spiral pattern of a first layer. The multi-layer spiral inductive array also includes a second multi-layer spiral inductor with a third layer matching a spiral pattern of a fourth layer. The second multi-layer spiral inductor is coupled in series with the first multi-layer spiral inductor.

Low DC resistance and high RF resistance power amplifier choke inductor

A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

Passive-on-glass (POG) device and method

Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

3D pillar inductor

An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.

Segmented thermal and RF ground

Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

Two-dimensional structure to form an embedded three-dimensional structure

In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.

Power amplifier with RF structure

Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes an IC and a shielding sidewall disposed adjacent to the IC. In certain aspects, the IC comprises a first layer coupled to the shielding sidewall, a second layer comprising a first signal path, and a third layer disposed below the first layer and coupled to the shielding sidewall, wherein the second layer is disposed between the first layer and the third layer. In some cases, the IC also includes a plurality of vias configured to couple the first layer to the third layer, wherein at least a portion of the first signal path is disposed in an inner shielding region that spans from the first layer to the third layer and spans from the shielding sidewall to the plurality of vias.

Waveguide along shielded side wall

A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

Land grid array (LGA) packaging of passive-on-glass (POG) structure

A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Varying thickness inductor

An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

Integrated circuits (ICs) on a glass substrate

An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

Solenoid inductor

A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

Backside drill embedded die substrate

Some features pertain to a stacked package apparatus that includes a shield at least partially surrounding the apparatus, a first substrate including a plurality of first pads, the plurality of first pads coupled to the shield, and a second substrate, the second substrate over the first substrate and coupled to the first substrate, the second substrate including a plurality of second pads, the plurality of second pads coupled to the shield.

Shielded stacked substrate apparatus and method of fabricating

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Del Mar, CA, United States of America

Daeik Daniel Kim