Samsung Electronics Co., Ltd.

Dae-Woo Kim

Hyuekjae Lee

Sang Cheon Park

Taehun Kim

Eunseok Song

Sangwon Kim

Un-Byoung Kang

Jongho Lee

Young Min Lee

Jong-Dae Park

Wonjae Lee

Hae-Jung Yu

Young Kun Jee

Hyuek Jae Lee

Chang-Hyun Lim

Sang-Kook Choi

Sang-woon Kim

Jae-kyung Lee

Jang-Hyeok Lee

Bon-rip Koo

Dae-Man Seo

A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

Semiconductor package

A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads

Heat treatment equipment and a method of driving the same are provided. The heat treatment equipment includes: a process tube having an aperture at one side thereof; a sealing unit for opening or closing the aperture; and a pressure sensor for measuring sealing pressure between the sealing unit and the one side of the process tube. In the heat treatment equipment, the aperture of the process tube can be sealed according to the sealing pressure of the sealing unit so that the process tube can be precisely sealed.

Heat treatment equipment and method of driving the same

A large diameter wafer conveying system includes a vacuum supplier and a valve unit for ON/OFF controlling a vacuum supplied from the vacuum supplier. A wafer holder stably absorbs and holds a wafer by using the vacuum supplied from the vacuum supplier through the valve unit. A residual vacuum clearer automatically clears a portion of the vacuum which remains after the valve unit is turned OFF to completely remove the vacuum.

Large diameter wafer conveying system and method thereof

A leakage gas detector for a semiconductor device includes a plurality of inflow apertures into which leakage gas flows. A detector sequentially detects the leakage gas in each of the inflow apertures via a plurality of valves, so as to leak test each of the plurality of inflow apertures for presence of possible leakage gas. Each of the plurality of valves are connected to corresponding of the plurality of inflow apertures to control the suction of the leakage gas into the detector. A controller selectively opens and closes each of the plurality of valves.

Growing community of inventors

Seongnam-si, South Korea

Dae-Woo Kim