Samsung Electronics Co., Ltd.

Dae-Won Ha

Gwan-Hyeob Koh

Byoung-Hak Hong

Sang-Yoon Kim

Gi-Tae Jeong

Sung-Sam Lee

Yong-Tae Kim

Sung-il Park

Yun-Gi Kim

Gyo-young Jin

Keun-Hwi Cho

Jung-hyuk Lee

Min-Young Shim

Mi-Youn Kim

Kwang-Jin Lee

Dong-won Kim

Sang-hyun Lee

Su-Jin Ahn

Chang-hyun Cho

Kong-Soo Lee

Hyeong-jun Kim

Hong-Sik Jeong

Dong-Won Shin

Kyu-Baik Chang

Tae-Hyun An

Mi-hyang Lee

Toshinori Fukai

Jung-Hyuk Lee

Mun-Hyeon Kim

Woong-Gi Kim

Bon-Woong Koo

Sue-Hye Park

Sang-Hyun Hong

An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.

Integrated circuit devices and methods of fabricating such devices

A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.

Semiconductor devices having dummy gate structure for controlling channel stress

Provided is a semiconductor device to which a pattern structure for performance improvement is applied. The semiconductor device includes first and second active regions spaced apart from each other in a first direction with an isolation layer interposed therebetween, a first normal gate formed on the first active region to extend in a second direction crossing the first direction, a first dummy gate having a portion overlapping with one end of the isolation layer and the other portion overlapping with the first active region and spaced apart from the first normal gate in the first direction, a second dummy gate having a portion overlapping with the other end of the isolation layer and the other portion overlapping with the second active region, a first normal source/drain contact formed on a source/drain region between the first normal gate and the first dummy gate, and a dummy contact formed on the isolation layer so as not to overlap with the first and second dummy gates and having a different size from the first normal source/drain contact.

Semiconductor device

A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material.

Methods of fabricating semiconductor device

The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.

Multi-level memory devices and methods of operating the same

In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.

Semiconductor device having recessed gate electrode and method of fabricating the same

A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

Semiconductor devices having resistors

A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

Phase change memory device and write method thereof

A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

Non-volatile memory devices including stacked NAND-type resistive memory cell strings

A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

Semiconductor device and method of fabricating the same

A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element hole on the second exposed portion of the semiconductor region. A surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate may have a same conductivity type. Related methods are also discussed.

Semiconductor devices having active elements with raised semiconductor patterns and related methods of fabricating the same

Methods of fabricating semiconductor devices having resistors

Growing community of inventors

Seoul, South Korea

Dae-Won Ha