Taiwan Semiconductor Manufacturing Comp. Ltd.

Da-Wen Lin

Chun Hsiung Tsai

Chien-Tai Chan

Yen-Chun Lin

Ming-Lung Cheng

Wei-Yang Lee

Chung-Cheng Wu

King-Yuen Wong

Kuo-Feng Yu

Wei-Yuan Lu

Yi-Ming Sheu

Tsung-Lin Lee

Chia-Pin Lin

Chia-Yu Lu

Li-Wen Weng

Clement Hsingjen Wann

Carlos H Diaz

Yu-Lien Huang

Shahaji B More

Tung Ying Lee

Cheng-Yi Peng

Chii-Ming M Wu

Ying-Keung Leung

Chih-Chieh Yeh

Jian-Hao Chen

Chien-Chang Su

Hsien-Chin Lin

Chia-Ming Hsu

Shyh-Wei Wang

Yin-Pin Wang

Yvonne Lin

Sheng-Jier Yang

Choh Fei Yeap

Paul Rousseau

Mao-Rong Yeh

Min Jiao

Peter Huang

Mei-Yun Wang

Xiong-Fei Yu

Kuang-Hsin Chen

Ming-Yuan Wu

Yi-Fang Pai

Li-Ping Huang

Chih-Hsiang Huang

Yi-Jing Li

Cheng-Ku Chen

Ying-Shiou Lin

Yi-Cheng Tsai

Chih-Hung Tseng

Tsung-Hung Li

Po-Ying Yeh

Shi-Shung Peng

Huicheng Chang

Chih-Hsin Ko

Chi-Hsi Wu

Chih Chieh Yeh

Ziwei Fang

Fu-Kai Yang

Chen-Ming Lee

Weng Chang

Ka-Hing Fung

Tsz-Mei Kwok

Chun-Feng Nieh

Tsan-Chun Wang

Yuan-Ching Peng

Yo-Sheng Lin

Chun-Hsiung Tsai

Hsien-Hsin Lin

Zhen-Cheng Wu

Ting-Yeh Chen

Wen-Sheh Huang

An-Shen Chang

Mong Song Liang

Ji-Yin Tsai

Hung-Ju Chou

Hung Chun Tsai

Chi-Hsun Hsieh

Yi-Ting Fu

Tsung-Hung Lee

Kao-Ting Lai

Shwang-Ming Cheng

Yi-Ling Chan

Ting Fang

Chia Ping Lo

Chung-Yu Chiang

Che-Min Chu

Wan-Yih Lien

Jerry Lai

Chih-hsin Ko

Hsu-Chieh Cheng

Wei-Yuan Jheng

Choh-Fei Yeap

A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

Method of fabricating a gate cut feature for multi-gate semiconductor devices

A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Multi-gate device and related methods

Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Device and method of fabricating multigate devices having different channel configurations

The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness ton the substrate at a second temperature T; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature Tless than T, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor layers.

Method and multi-channel devices with anti-punch-through features

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature Tis lower than the temperature T

Semiconductor devices with low leakage current and methods of fabricating the same

A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

Semiconductor structure and method for forming the same

Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.

Manufacturing method for semiconductor structure having a plurality of fins

Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Source/drain contact with low-k contact etch stop layer and method of fabricating thereof

A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

FinFET fabrication methods

A semiconductor device includes a substrate, an isolation structure, a semiconductor fin, a semiconductor layer, and a gate structure. The isolation structure is disposed over the substrate. The semiconductor fin extends from the substrate and in contact with the isolation structure. The semiconductor layer is disposed on and in contact with the isolation structure. The gate structure covers the semiconductor layer and spaced apart from the semiconductor fin.

Semiconductor device and manufacturing method thereof

Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

Semiconductor structure having fin with all around gate

A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

FinFET device with different liners for PFET and NFET and method of fabricating thereof

A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

Fin field effect transistor (FinFET) device structure with deep contact structure

Growing community of inventors

Hsinchu, Taiwan

Da-Wen Lin