National Semiconductor Corporation

Texas Instruments Corporation

D Courtney Parker

William David French

Constantin Bulucea

Sandeep Raj Bahl

Jeng-Jiun Yang

Donald M Archer

Peter B Johnson

Prasad Chaparala

An insulated-gate field-effect transistor (110, 114, or 122) is fabricated so that its gate dielectric layer (or) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (or) from significantly penetrating through the gate dielectric layer into the underlying channel zone (or) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.

Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile

An asymmetric insulated-gate field-effect transistor (or) has a source (or) and a drain (or) laterally separated by a channel zone (or) of body material (or) of a semiconductor body. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A more heavily doped pocket portion (or) of the body material extends largely along only the source. The source has a main source portion (M orM) and a more lightly doped lateral source extension (E orE). The drain has a main portion (M orM) and a more lightly doped lateral drain extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions

Insulated-gate field-effect transistors ('IGFETs'), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (, or) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (, or). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (, or) has a main portion (M,M,M,M,M,M,M,M,M,M,M, orM) and a more lightly doped lateral extension (E,E,E,E,E,E,E,E,E,E,E, orE). Alternatively or additionally, a more heavily doped pocket portion (or) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.

Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket

A group of high-performance like-polarity insulated-gate field-effect transistors (, andor, and) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors ('IGFETs'), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and) utilize empty wells (, and) in achieving desired transistor characteristics. Other IGFETs (, and) utilize filled wells (, and) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Configuration and fabrication of semiconductor structure using empty and filled wells

A gate dielectric layer (, or) of an insulated-gate field-effect transistor (, or) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (, or) from significantly penetrating through the gate dielectric layer into the underlying channel zone (, or) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.

A gate electrode () of a field-effect transistor () is defined above, and vertically separated by a gate dielectric layer () from, a channel-zone portion () of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion () using the gate electrode as a dopant-blocking shield. A spacer (T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (M andM) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (). Electrical contacts (and) are formed respectively to the source/drain portions.

Fabrication of asymmetric field-effect transistors using L-shaped spacers

An asymmetric insulated-gate field-effect transistor () has a source () and a drain () laterally separated by a channel zone () of body material () of a semiconductor body. A gate electrode () overlies a gate dielectric layer () above the channel zone. A more heavily doped pocket portion () of the body material extends largely along only the source. Each of the source and drain has a main portion (M orM) and a more lightly doped lateral extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

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D Courtney Parker